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PDF XCR3128A Data sheet ( Hoja de datos )
| Número de pieza | XCR3128A | |
| Descripción | CPLD with Enhanced Clocking | |
| Fabricantes | Xilinx | |
| Logotipo |  |
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APPLICATION NOTE
0
XCR3128A: 128 Macrocell
CPLD with Enhanced Clocking
DS035 (v1.2) August 10, 2000
0 14* Product Specification
Features
• Industry's first TotalCMOS™ PLD - both CMOS design
and process technologies
• Fast Zero Power (FZP™) design technique provides
ultra-low power and very high speed
• 3V, In-System Programmable (ISP) using a JTAG
interface
- On-chip supervoltage generation
- ISP commands include: Enable, Erase, Program,
Verify
- Supported by multiple ISP programming platforms
- 4-pin JTAG interface (TCK, TMS, TDI, TDO)
- JTAG commands include: Bypass, Idcode
• High-speed pin-to-pin delays of 7.5 ns
• Ultra-low static power of less than 100 µA
• 5V tolerant I/Os to support mixed voltage systems
• 100% routable with 100% utilization while all pins and
all macrocells are fixed
• Deterministic timing model that is extremely simple to
use
• Up to 20 clocks available
• Support for complex asynchronous clocking
• Innovative XPLA™ architecture combines high-speed
with extreme flexibility
• 1000 erase/program cycles guaranteed
• 20 years data retention guaranteed
• Logic expandable to 37 product terms
• Advanced 0.35µ E2CMOS process
• Security bit prevents unauthorized access
• Design entry and verification using industry standard
and Xilinx CAE tools
• Reprogrammable using industry standard device
programmers
• Innovative Control Term structure provides either sum
terms or product terms in each logic block for:
- Programmable 3-state buffer
- Asynchronous macrocell register preset/reset
- Up to two, asynchronous clocks
• Programmable global 3-state pin facilitates "bed of
nails" testing without using logic resources
• Available in TQFP and VQFP packages
• Available in both commercial and industrial grades
• Industrial grade operates from 2.7V to 3.6V
Description
The XCR3128A CPLD (Complex Programmable Logic
Device) is a member of the CoolRunner® family of CPLDs
from Xilinx. These devices combine high speed and zero
power in a 128 macrocell CPLD. With the FZP design tech-
nique, the XCR3128A offers true pin-to-pin speeds of 7.5
ns, while simultaneously delivering power that is less than
100 µA at standby without the need for ‘turbo bits' or other
power-down schemes. By replacing conventional sense
amplifier methods for implementing product terms (a tech-
nique that has been used in PLDs since the bipolar era)
with a cascaded chain of pure CMOS gates, the dynamic
power is also substantially lower than any competing
CPLD. These devices are the first TotalCMOS PLDs, as
they use both a CMOS process technology and the pat-
ented full CMOS FZP design technique.
The Xilinx FZP CPLDs utilize the patented XPLA
(eXtended Programmable Logic Array) architecture. The
XPLA architecture combines the best features of both PLA
and PAL type structures to deliver high-speed and flexible
logic allocation that results in superior ability to make
design changes with fixed pinouts. The XPLA structure in
each logic block provides a fast 7.5 ns PAL path with five
dedicated product terms per output. This PAL path is joined
by an additional PLA structure that deploys a pool of 32
product terms to a fully programmable OR array that can
allocate the PLA product terms to any output in the logic
block. This combination allows logic to be allocated effi-
ciently throughout the logic block and supports as many as
37 product terms on an output. The speed with which logic
is allocated from the PLA array to an output is only 1.5 ns,
regardless of the number of PLA product terms used, which
results in worst case tPD's of only 9 ns from any pin to any
other pin. In addition, logic that is common to multiple out-
puts can be placed on a single PLA product term and
shared across multiple outputs via the OR array, effectively
increasing design density.
The XCR3128A CPLDs are supported by industry standard
CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Syn-
opsys, Synario, Viewlogic, and Synplicity), using text
(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-
ification uses industry standard simulators for functional
and timing simulation. Development is supported on per-
sonal computer, Sparc, and HP platforms. Device fitting
uses a Xilinx developed tool, XPLA Professional (available
on the Xilinx web site).
DS035 (v1.2) August 10, 2000
www.xilinx.com
1-800-255-7778
1
1 page  
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
R
Simple Timing Model
Figure 4 shows the CoolRunner Timing Model. The Cool-
Runner timing model looks very much like a 22V10 timing
model in that there are three main timing parameters,
including tPD, tSU, and tCO. In other competing architec-
tures, the user may be able to fit the design into the CPLD,
but is not sure whether system timing requirements can be
met until after the design has been fit into the device. This is
because the timing models of competing architectures are
very complex and include such things as timing dependen-
cies on the number of parallel expanders borrowed, shar-
able expanders, varying number of X and Y routing
channels used, etc. In the XPLA architecture, the user
knows up front whether the design will meet system timing
requirements. This is due to the simplicity of the timing
model.
INPUT PIN
INPUT PIN
tPD_PAL = COMBINATORIAL PAL ONLY
tPD_PLA = COMBINATORIAL PAL + PLA
REGISTERED
tSU_PAL = PAL ONLY
tSU_PLA = PAL + PLA
D
REGISTERED
Q tCO
OUTPUT PIN
OUTPUT PIN
GLOBAL CLOCK PIN
Figure 4: CoolRunner Timing Model
SP00553
5
www.xilinx.com
DS035 (v1.2) August 10, 2000
1-800-255-7778
5 Page 
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
R
Absolute Maximum Ratings1
Symbol
Parameter
Min.
Max.
Unit
VCC Supply voltage 2
-0.5 4.6
V
VI Input voltage
-1.2 5.75
V
VOUT
Output voltage
-0.5 5.5
V
IIN Input current
-30 30 mA
TJ Maximum junction temperature
-40 150 °C
Tstr Storage temperature
-65 150 °C
Notes:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only.
Functional operation at these or any other condition above those indicated in the operational and programming specification
is not implied.
2. The chip supply voltage must rise monotonically.
Operating Range
Product Grade
Commercial
Industrial
Temperature
0 to +70°C
-40 to +85°C
Voltage
3.0 to 3.6 V
2.7 to 3.6 V
DC Electrical Characteristics For Commercial Grade Devices
Commercial: 0°C ≤ TAMB ≤ +70°C; 3.0V ≤ VCC ≤ 3.6V
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VIL Input voltage Low
VCC = 3.0V
0.8 V
VIH Input voltage High
VCC = 3.6V
2.0 V
VI Input clamp voltage
VCC = 3.0V, IIN = -18 mA
-1.2 V
VOL Output voltage Low
VCC = 3.0V, IOL = 12 mA
0.5 V
VOH Output voltage High
VCC = 3.0V, IOH = -12 mA
2.4
V
II Input leakage current
VIN = 0 to 5.5V
-10 10 µA
IOZ
ICCQ1
ICCD 1, 2
3-stated output leakage current
Standby current
Dynamic current
VIN = 0 to 5.5V
VCC = 3.6V, TAMB = 0°C
VCC = 3.6V, TAMB = 0°C @ 1 MHz
-10 10 µA
100 µA
2 mA
VC = 3.6V, TAMB = 0°C @ 50 MHz
50 mA
IOS
Short circuit output current 3
One pin at a time for no longer than one -50
-200
mA
second
CIN
CCLK
CI/O
Input pin capacitance 3
Clock input capacitance 3
I/O pin capacitance3
TAMB = 25°C, f = 1 MHz
TAMB = 25°C, f = 1 MHz
TAMB = 25°C, f = 1 MHz
8 pF
5 12 pF
10 pF
Notes:
1. See Table 2 on page 7 typical values.
2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled
and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.
3. Typical values, not tested.
11
www.xilinx.com
DS035 (v1.2) August 10, 2000
1-800-255-7778
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet XCR3128A.PDF ] | |
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