DataSheetWiki


XCR3064XL-6PC44C fiches techniques PDF

Xilinx - XCR3064XL 64 Macrocell CPLD

Numéro de référence XCR3064XL-6PC44C
Description XCR3064XL 64 Macrocell CPLD
Fabricant Xilinx 
Logo Xilinx 





1 Page

No Preview Available !





XCR3064XL-6PC44C fiche technique
0
R XCR3064XL 64 Macrocell CPLD
DS017 (v1.6) January 8, 2002
0 14 Product Specification
Features
• Lowest power 64 macrocell CPLD
• 6.0 ns pin-to-pin logic delays
• System frequencies up to 145 MHz
• 64 macrocells with 1,500 usable gates
• Available in small footprint packages
- 44-pin PLCC (36 user I/O pins)
- 44-pin VQFP (36 user I/O pins)
- 48-ball CS BGA (40 user I/O pins)
- 56-ball CP BGA (48 user I/O pins)
- 100-pin VQFP (68 user I/O pins)
• Optimized for 3.3V systems
- Ultra-low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- Fast Zero Power™ (FZP) CMOS design
technology
• Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 available clocks per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
• Fast ISP programming times
• Port Enable pin for dual function of JTAG ISP pins
• 2.7V to 3.6V supply voltage at industrial temperature
range
• Programmable slew rate control per macrocell
• Security bit prevents unauthorized access
• Refer to XPLA3 family data sheet (DS012) for
architecture description
Description
The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of four function blocks provide
1,500 usable gates. Pin-to-pin propagation delays are
6.0 ns with a maximum system frequency of 145 MHz.
TotalCMOS Design Technique for Fast
Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1 and Table 1 showing the ICC vs. Frequency of our
XCR3064XL TotalCMOS CPLD (data taken with four
resetable up/down, 16-bit counters at 3.3V, 25°C).
35.0
30.0
25.0
20.0
15.0
10.0
5.0
0.0
0 20 40 60 80 100 120 140
Frequency (MHz)
DS017_01_102401
Figure 1: ICC vs. Frequency at VCC = 3.3V, 25°C
Table 1: ICC vs. Frequency (VCC = 3.3V, 25°C)
Frequency (MHz) 0 1 5 10 20 40 60 80 100 120 140
Typical ICC (mA)
0
0.2 1.0 2.0 3.9 7.6 11.3 14.8 18.5 22.1 25.6
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS017 (v1.6) January 8, 2002
Product Specification
www.xilinx.com
1-800-255-7778
1

PagesPages 9
Télécharger [ XCR3064XL-6PC44C ]


Fiche technique recommandé

No Description détaillée Fabricant
XCR3064XL-6PC44C XCR3064XL 64 Macrocell CPLD Xilinx
Xilinx
XCR3064XL-6PC44I XCR3064XL 64 Macrocell CPLD Xilinx
Xilinx

US18650VTC5A

Lithium-Ion Battery

Sony
Sony
TSPC106

PCI Bus Bridge Memory Controller

ATMEL
ATMEL
TP9380

NPN SILICON RF POWER TRANSISTOR

Advanced Semiconductor
Advanced Semiconductor


www.DataSheetWiki.com    |   2020   |   Contactez-nous  |   Recherche