PDF XCCACE128-I Data sheet ( Hoja de datos )

Número de pieza	XCCACE128-I
Descripción	System ACE CompactFlash Solution
Fabricantes	Xilinx
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No Preview Available ! 0 R System ACE CompactFlash Solution DS080 (v1.4) January 3, 2002 00 Features • System-Level Features: - High-capacity pre-engineered configuration solution for FPGAs - Chipset configuration solution: · ACE™ Controller – Configuration manager · ACE Flash – High-capacity CompactFlash™ storage device - Non-volatile system solution - Flexible configuration interfaces - System configuration rates of up to 30 Mb/s - Board space requirement as low as 25 cm2 • ACE Flash (Xilinx-supplied Flash Cards): - Densities of 128 Mbits and 256 Mbits - CompactFlash Type I form factor - PC Card ATA protocol compatible - Noiseless and low CMOS power - Automatic error correction and write retry capabilities - Multiple partitions - Program/erase over full commercial/industrial temperature range Advance Product Specification - Removable storage device - Excellent quality and reliability · MTBF >1,000,000 hours · Minimum 10,000 insertions • ACE Controller: - CompactFlash interface supports ACE Flash cards, standard third-party CompactFlash (Type I or Type II) cards, and IBM Microdrives with up to 8 Gbit capacity - Configuration of a target FPGA chain through IEEE 1149.1 JTAG with a throughput up to 16.7 Mbits/sec - Interfaces include CompactFlash, JTAG, and MPU - MPU interface is compatible with microprocessor/ microcontroller bus interfaces, such as the IBM PPC405, and Siemens 80C166 - IEEE 1149.1 Boundary-Scan Standard Compliant (JTAG) - FAT12/16 file system - Compact 144-pin TQFP package - Low power General Description Xilinx developed the System Advanced Configuration Envi- ronment (System ACE) family to address the need for a space-efficient, pre-engineered, high-density configuration solution for systems with multiple FPGAs. System ACE technology is a ground-breaking in-system programmable configuration solution that provides substantial savings in development effort and cost per bit over traditional PROM and embedded solutions for high-capacity FPGA systems. The System ACE family combines Xilinx expertise in config- uration control with industry expertise in commodity memo- ries. The first member of the System ACE family uses CompactFlash. As shown in Figure 1, the System ACE CompactFlash solu- tion is a chipset, consisting of a controller device (ACE Con- troller) and a CompactFlash storage device (ACE Flash). ACE Flash CompactFlash Storage Device System ACE Controller Device 128 Mbits or 256 Mbits Interface to FPGA Target Chain from CompactFlash, MPU, or Test JTAG Port Figure 1: System ACE Chipset DS080_01_032101 © 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS080 (v1.4) January 3, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 1 1 page R System ACE CompactFlash Solution I Shaded output buffers drive VOH = VCCL = 2.5V or 3.3V I Shaded input buffers sense VIH = VCCL = 2.5V or 3.3V I All non-shaded output buffers drive VOH = VCCH = 3.3V I All non-shaded input buffers sense VIH = VCCH = 3.3V I "LS" denotes level-shifter I Core voltage level = VCCL = 2.5V or 3.3V CompactFlash LS LS LS LS CORE CFGJTAG Figure 5: ACE Controller I/O Requirements Status Indicators The ACE Controller has indicator pins to help monitor device status during operation. DS080_05_030801 Table 2: ACE Controller Status Indicators Name Pin Description STATLED ERRLED • When on, the Status LED indicates that configuration is DONE. 95 • When blinking, this LED indicates that configuration is still in progress. • When off this LED indicates that configuration is in an IDLE state. • When on, the ERROR LED indicates that an error occurred. 96 • When blinking, this LED indicates that no CompactFlash device was found when the CompactFlash for the Configuration JTAG interface was enabled. • When off, this LED indicates that no errors are detected. DS080 (v1.4) January 3, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 5 5 Page R System ACE CompactFlash Solution MPU Timing Description This section contains timing diagrams for the MPU interface. Parameters used in the timing diagrams are described in Table 7. Table 7: MPU Interface Timing Parameters Symbol Parameter Min Max Units tSA Address setup time 4 -- ns tSCE Chip enable setup time 4 -- ns tSWE Write enable setup time 12 -- ns tSOE Output enable setup time 12 -- ns tSD Data setup time 4 -- ns tDD Clock HIGH to valid data -- 22 ns tDOE Chip/Output enable LOW to valid data -- 13 ns tDBRDY Clock HIGH to buffer ready valid -- 22 ns tH Hold time 0 -- ns Single Register Read Cycle The single register read cycle is shown in Figure 10. A sin- gle register read is accomplished by asserting a valid address (MPA), asserting the chip enable (MPCE = LOW) and de-asserting the write enable (MPWE = HIGH) during the first clock cycle (Cycle 0). These signals should hold these values at least until the rising edge of the fourth clock cycle (Cycle 3). The output enable signal should be asserted (MPOE = LOW) during the third clock cycle (Cycle 2). Register data associated with the specified address appears on the MPD bus two clock cycles after the falling edge of MPCE during the assertion of MPCE. The register read cycle is then com- pleted by de-asserting the output enable during the fourth clock cycle (Cycle 3). CYCLE CLK MPA MPD MPCE MPWE MPOE 40ns Cycle 0 60ns 80ns Cycle 1 100ns Cycle 2 120ns 140ns 160 Cycle 3 Cycle 4 tSA ADDRESS tSCE tDOE tDD DATA tH tDD tDOE tH tSWE tH tDOE tSOE tDOE tH tSOE tH Figure 10: Single Read From an ACE Register DS080_14_013101 DS080 (v1.4) January 3, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 11 11 Page

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