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PDF XC95288-20HQ208C Data sheet ( Hoja de datos )
| Número de pieza | XC95288-20HQ208C | |
| Descripción | XC95288XL High Performance CPLD | |
| Fabricantes | Xilinx | |
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0
R XC95288XL High Performance
CPLD
DS055 (v1.5) June 20, 2002
0 5 Product Specification
Features
• 6 ns pin-to-pin logic delays
• System frequency up to 208 MHz
• 288 macrocells with 6,400 usable gates
• Available in small footprint packages
- 144-pin TQFP (117 user I/O pins)
- 208-pin PQFP (168 user I/O pins)
- 256-pin BGA (192 user I/O pins)
- 256-pin FBGA (192 user I/O pins)
- 280-pin CSP (192 user I/O pins)
• Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
• Advanced system features
- In-system programmable
- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin with local
inversion
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
• Pin-compatible with 5V-core XC95288 device in the
208-pin HQFP package
Description
The XC95288XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of 16
54V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 6 ns. See Figure 2 for architecture
overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of ICC, the following equation may be
used:
ICC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP
+ 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f
where:
MCHS = # macrocells in high-speed configuration
PTHS = average number of high-speed product terms
per macrocell
MCLP = # macrocells in low power configuration
PTLP = average number of low power product terms per
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual ICC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
application note XAPP114, “Understanding XC9500XL
CPLD Power.”
550
208 MHz
500
450
400
350
High Performance
300
250
200
Low Power
94 MHz
150
100
50
0
50
100 150
200 250
Clock Frequency (MHz)
DS055_01_121501
Figure 1: Typical ICC vs. Frequency for XC95288XL
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS055 (v1.5) June 20, 2002
Product Specification
www.xilinx.com
1-800-255-7778
1
1 page  
R XC95288XL High Performance CPLD
Internal Timing Parameters
Symbol
Parameter
Buffer Delays
TIN
TGCK
TGSR
TGTS
TOUT
TEN
Input buffer delay
GCK buffer delay
GSR buffer delay
GTS buffer delay
Output buffer delay
Output buffer enable/disable
delay
Product Term Control Delays
TPTCK Product term clock delay
TPTSR Product term set/reset delay
TPTTS Product term 3-state delay
Internal Register and Combinatorial Delays
TPDI Combinatorial logic propagation delay
TSUI Register setup time
THI Register hold time
TECSU Register clock enable setup time
TECHO Register clock enable hold time
TCOI Register clock to output valid time
TAOI Register async. S/R to output delay
TRAI Register async. S/R recover before clock
TLOGI Internal logic delay
TLOGILP Internal low power logic delay
Feedback Delays
TF Fast CONNECT II feedback delay
Time Adders
TPTA Incremental product term allocator delay
(first incremental delay)
TPTA2 Incremental product term allocator delay
(subsequent incremental delay)
TSLEW Slew-rate limited delay
XC95288XL-6
Min Max
XC95288XL-7
Min Max
XC95288XL-10
Min Max Units
- 2.2 - 2.3 - 3.5 ns
- 1.2 - 1.5 - 1.8 ns
- 2.2 - 3.1 - 4.5 ns
- 4.5 - 5.0 - 7.0 ns
- 2.4 - 2.5 - 3.0 ns
- 0 - 0 - 0 ns
- 2.0 - 2.4 - 2.7 ns
- 1.0 - 1.4 - 1.8 ns
- 6.2 - 7.2 - 7.5 ns
- 0.4 - 1.3 - 1.7 ns
2.0 - 2.6 - 3.0 - ns
1.6 - 2.2 - 3.5 - ns
2.0 - 2.6 - 3.0 - ns
1.6 - 2.2 - 3.5 - ns
- 0.2 - 0.5 - 1.0 ns
- 6.2 - 6.4 - 7.0 ns
6.0 7.5 10.0 ns
- 1.0 - 1.4 - 1.8 ns
- 5.5 - 6.4 - 7.3 ns
- 1.6 - 3.5 - 4.2 ns
- 0.8 - 0.8 - 1.0 ns
- 0.3 - 0.3 - 0.4 ns
- 3.5 - 4.0 - 4.5 ns
DS055 (v1.5) June 20, 2002
Product Specification
www.xilinx.com
1-800-255-7778
5
5 Page 
R
Ordering Information
Example: XC95288XL -6 TQ 144 C
Device Type
Speed Grade
XC95288XL High Performance CPLD
Temperature Range
Number of Pins
Package Type
Device Ordering Options
Speed
Package
-10 10 ns pin-to-pin delay
-7 7.5 ns pin-to-pin delay
-6 6 ns pin-to-pin delay
TQ144 144-pin Thin Quad Flat Pack (TQFP)
PQ208 208-pin Plastic Quad Flat Pack (PQFP)
BG256 256-pin Plastic Ball Grid Array (BGA)
FG256 256-pin Plastic Fine-Pitch Ball Grid
Array (FBGA)
CS280 280-pin Chip Scale Package (CSP)
Temperature
C = Commercial
I = Industrial
TA = 0°C to +70°C
TA = –40°C to +85°C
Component Availability
Pins
144 208 256
Type
Plastic TQFP Plastic PQFP Plastic BGA
Code
TQ44
PQ208
BG256
XC95288XL
-10
C, I
C, I C, I
-7 C, I
C, I C, I
-6 C
CC
Notes:
1. C = Commercial (TA = 0oC to +70oC); I = Industrial (TA = –40oC to +85oC).
256
Plastic FBGA
FG256
C, I
C, I
C
280
Plastic CSP
CS280
C, I
C, I
C
Revision History
The following table shows the revision history for this document.
Date
09/28/98
02/05/99
06/07/99
02/08/01
03/19/01
06/20/02
Version
1.0
1.1
1.2
1.3
1.4
1.5
Revision
Initial Xilinx release.
Updateed pinouts to reflect BG256 (replaces BG352).
Added -7 speed and CS280 package.
Updated -6 AC and timing parameters, added FG256 package.
Pinout corrections.
Updated ICC equation, page 1. Updated Component Availability Chart: added -7 Industrial.
Added additional IIH test conditions and measurements to DC Characteristics table.
DS055 (v1.5) June 20, 2002
Product Specification
www.xilinx.com
1-800-255-7778
11
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