DataSheetWiki


XC95108-15TQ100C fiches techniques PDF

Xilinx - XC95108 In-System Programmable CPLD

Numéro de référence XC95108-15TQ100C
Description XC95108 In-System Programmable CPLD
Fabricant Xilinx 
Logo Xilinx 





1 Page

No Preview Available !





XC95108-15TQ100C fiche technique
1
® XC95108 In-System Programmable
CPLD
December 4, 1998 (Version 3.0)
1 1* Product Specification
Features
• 7.5 ns pin-to-pin logic delays on all pins
• fCNT to 125 MHz
• 108 macrocells with 2400 usable gates
• Up to 108 user I/O pins
• 5 V in-system programmable (ISP)
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs
• 3.3 V or 5 V I/O capability
• Advanced CMOS 5V FastFLASH technology
• Supports parallel programming of more than one
XC9500 concurrently
• Available in 84-pin PLCC, 100-pin PQFP, 100-pin TQFP
and 160-pin PQFP packages
Description
The XC95108 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of six
36V18 Function Blocks, providing 2,400 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC95108 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC95108
device.
300
200
(180)
100
High Performance
Low Power
(250)
(170)
0 50 100
Clock Frequency (MHz)
X5898
Figure 1: Typical ICC vs. Frequency for XC95108
December 4, 1998 (Version 3.0)
1

PagesPages 8
Télécharger [ XC95108-15TQ100C ]


Fiche technique recommandé

No Description détaillée Fabricant
XC95108-15TQ100C XC95108 In-System Programmable CPLD Xilinx
Xilinx
XC95108-15TQ100I XC95108 In-System Programmable CPLD Xilinx
Xilinx

US18650VTC5A

Lithium-Ion Battery

Sony
Sony
TSPC106

PCI Bus Bridge Memory Controller

ATMEL
ATMEL
TP9380

NPN SILICON RF POWER TRANSISTOR

Advanced Semiconductor
Advanced Semiconductor


www.DataSheetWiki.com    |   2020   |   Contactez-nous  |   Recherche