XC9144-10PQ100I Datasheet PDF - Xilinx
| Part Number | XC9144-10PQ100I | |
| Description | XC95144 In-System Programmable CPLD | |
| Manufacturers | Xilinx | |
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1
® XC95144 In-System Programmable
CPLD
December 4, 1998 (Version 4.0)
1 1* Product Specification
Features
• 7.5 ns pin-to-pin logic delays on all pins
• fCNT to 111 MHz
• 144 macrocells with 3,200 usable gates
• Up to 133 user I/O pins
• 5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs
• 3.3 V or 5 V I/O capability
• Advanced CMOS 5V FastFLASH technology
• Supports parallel programming of more than one
XC9500 concurrently
• Available in 100-pin PQFP, 100-pin TQFP, and 160-pin
PQFP packages
Description
The XC95144 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC95144 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC95144
device.
600
400
(300)
200
(160)
High Performance
Low Power
(480)
(320)
0 50 100
Clock Frequency (MHz)
X5898B
Figure 1: Typical Icc vs. Frequency for XC95144
December 4, 1998 (Version 4.0)
1
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XC95144 In-System Programmable CPLD
Device Output
VTEST
R1
R2
Output Type
VCCIO
5.0 V
VTEST
5.0 V
R1
160 Ω
R2
120 Ω
CL
35 pF
3.3 V
3.3 V
260 Ω
360 Ω
35 pF
CL X5906
Figure 3: AC Load Circuit
Internal Timing Parameters
Symbol
Parameter
Buffer Delays
tIN Input buffer delay
tGCK
GCK buffer delay
tGSR
GSR buffer delay
tGTS
GTS buffer delay
tOUT
Output buffer delay
tEN Output buffer enable/disable delay
Product Term Control Delays
tPTCK
Product term clock delay
tPTSR
Product term set/reset delay
tPTTS
Product term 3-state delay
Internal Register and Combinatorial delays
tPDI Combinatorial logic propagation delay
tSUI Register setup time
tHI Register hold time
tCOI Register clock to output valid time
tAOI Register async. S/R to output delay
tRAI Register async. S/R recovery before clock
tLOGI
Internal logic delay
tLOGILP Internal low power logic delay
Feedback Delays
tF FastCONNECT matrix feedback delay
tLF Function Block local feedback delay
Time Adders
tPTA3
tSLEW
Incremental Product Term Allocator delay
Slew-rate limited delay
XC95144-7
Min Max
2.5
1.5
4.5
5.5
2.5
0.0
3.0
2.0
4.5
0.5
1.5
3.0
0.5
6.5
7.5
2.0
10.0
8.0
4.0
1.0
4.0
XC95144-10
Min Max
3.5
2.5
6.0
6.0
3.0
0.0
3.0
2.5
3.5
2.5
3.5
10.0
1.0
0.5
7.0
2.5
11.0
9.5
3.5
1.0
4.5
XC95144-15
Units
Min Max
4.5
3.0
7.5
11.0
4.5
0.0
ns
ns
ns
ns
ns
ns
2.5 ns
3.0 ns
5.0 ns
3.5
4.5
10.0
3.0
0.5
8.0
3.0
11.5
ns
ns
ns
ns
ns
ns
ns
ns
11.0 ns
3.5 ns
1.0 ns
5.0 ns
Note: 3. tPTA is multiplied by the span of the function as defined in the family data sheet.
December 4, 1998 (Version 4.0)
5
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