PDF XC73144 Data sheet ( Hoja de datos )

Número de pieza	XC73144
Descripción	144-Macrocell CMOS EPLD
Fabricantes	Xilinx
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No Preview Available ! ® XC7300 CMOS EPLD Family Product Description Features • High-performance Erasable Programmable Logic Devices (EPLDs) – 5 / 7.5 ns pin-to-pin speeds on all fast inputs – Up to 167 MHz maximum clock frequency • Advanced Dual-Block architecture – Fast Function Blocks – High-Density Function Blocks (XC7354, XC7372, XC73108, XC73144) • 100% interconnect matrix • High-speed arithmetic carry network – 1 ns ripple-carry delay per bit – 43 to 61 MHz 18-bit accumulators • Multiple independent clocks • Each input programmable as direct, latched, or registered • High-drive 24 mA output • I/O operation at 3.3 V or 5 V • Meets JEDEC Standard (8-1A) for 3.3 V ±0.3 V • Power management options • Multiple security bits for design protection • Supported by industry standard design and verification tools • 100% PCI compliant Description The XC7300 family employs a unique Dual-Block architec- ture, which provides high speed operations via Fast Func- tion Blocks and/or high density capability via High Density Function Blocks. Fast Function Blocks (FFBs) provide fast, pin-to-pin speed and logic throughput for critical decoding and ultra- fast state machine applications. High-Density Function Blocks (FBs) provide maximum logic density and system- level features to implement complex functions with pre- dictable timing for adders and accumulators, wide func- tions and state machines requiring large numbers of product terms, and other forms of complex logic. In addition, the XC7300 architecture employs the Univer- sal Interconnect Matrix (UIM) which guarantees 100% interconnect of all internal functions. This interconnect scheme provides constant, short interconnect delays for all routing paths through the UIM. Constant interconnect delays simplify device timing and guarantee design perfor- mance, regardless of logic placement within the chip. All XC7300 devices are designed in 0.8µ CMOS EPROM technology. All XC7300 EPLDs include programmable power manage- ment features to specify high-performance or low-power operation on an individual Macrocell-by-Macrocell basis. Unused Macrocells are automatically turned off to mini- The XC7300 Family Typical 22V10 Equivalent Number of Macrocells Number of Function Blocks Number of Flip-Flops Number of Fast Inputs Number of Signal Pins XC7318 1.5 – 2 18 2 18 12 38 XC7336 3–4 36 4 36 12 38 XC7354 6 54 6 108 12 58 XC7372 8 72 8 126 12 84 XC73108 12 108 12 198 12 120 XC73144 16 144 16 276 12 156 2-1 This document was created with FrameMaker 4 0 2 1 page 21 Inputs from UIM 3 from Fast Input Pins (FI) AND Array 12 Sharable 5 Private P-Terms per P-Terms per Function Block Macrocell 4 8 5 Arithmetic Carry-In from Previous Macrocell Fast Clocks 01 CLOCK OE* SET RESET C in D1 F D2 C out ALU 1 of 9 Macrocells RS DQ To 8 More Macrocells Shift-In from Previous MC Shift-Out to Next MC Local Feedback Clock Select Register Trasparent Control Feedback Polarity * OE is forced high when P-term is not used Arithmetic Carry-Out to Next Macrocell Feedback to UIM Input to UIM Feedback Enable Override Global Fast OE I/O (see fig.7) OE Control Input-Pad Register/Latch (optional) Pin X5485 Figure 5. High-Density Function Block and Macrocell Schematic Table 1. Function Generator Logic Operations D1:+: D2 D1 * D2 D1 + D2 D1 D1 D1 * D2 D1 + D2 Function D1:+: D2 D1 * D2 D1 + D2 D2 D2 D1 * D2 D1 + D2 Arithmetic Logic Unit (ALU) D1 Sum-of- Products D2 Sum-of- Products D1 Function Generator D2 Carry Output 0 1 To Macrocell Flip-Flop Therefore, the ALU can implement one additional layer of logic without any speed penalty. In arithmetic mode, the ALU block can be programmed to generate the arithmetic sum or difference of the D1 and D2 inputs. Combined with the carry input from the next lower Macrocell, the ALU operates as a 1-bit full adder generating a carry output to the next higher Macrocell. The carry chain propagates between adjacent Macrocells and also crosses the boundaries between Function Blocks. This dedicated carry chain overcomes the inher- ent speed and density problems of the traditional EPLD architecture when trying to perform arithmetic functions. Carry Lookahead Each Function Block provides a carry lookahead genera- tor capable of anticipating the carry across all nine Mac- rocells. The carry lookahead generator reduces the ripple-carry delay of wide arithmetic functions such as add, subtract, and magnitude compare to that of the ﬁrst nine bits, plus the carry lookahead delay of the higher- order Function Blocks. Arithmetic Carry Control Figure 6. ALU Schematic Carry Input Macrocell Flip-Flop The ALU block output drives the input of a programmable X3206 D-type ﬂip-ﬂop. The ﬂip-ﬂop is triggered by the rising edge of the clock input, but it can be conﬁgured as transparent, 2-5 5 Page

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