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Xilinx - Field Programmable Gate Arrays

Numéro de référence XC5202-6PQ100C
Description Field Programmable Gate Arrays
Fabricant Xilinx 
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XC5202-6PQ100C fiche technique
0
R XC5200 Series
Field Programmable Gate Arrays
November 5, 1998 (Version 5.2)
0 7* Product Specification
Features
• Low-cost, register/latch rich, SRAM based
reprogrammable architecture
- 0.5µm three-layer metal CMOS process technology
- 256 to 1936 logic cells (3,000 to 23,000 “gates”)
- Price competitive with Gate Arrays
• System Level Features
- System performance beyond 50 MHz
- 6 levels of interconnect hierarchy
- VersaRingI/O Interface for pin-locking
- Dedicated carry logic for high-speed arithmetic
functions
- Cascade chain for wide input functions
- Built-in IEEE 1149.1 JTAG boundary scan test
circuitry on all I/O pins
- Internal 3-state bussing capability
- Four dedicated low-skew clock or signal distribution
nets
• Versatile I/O and Packaging
- Innovative VersaRingI/O interface provides a high
logic cell to I/O ratio, with up to 244 I/O signals
- Programmable output slew-rate control maximizes
performance and reduces noise
- Zero Flip-Flop hold time for input registers simplifies
system timing
- Independent Output Enables for external bussing
- Footprint compatibility in common packages within
the XC5200 Series and with the XC4000 Series
- Over 150 device/package combinations, including
advanced BGA, TQ, and VQ packaging available
• Fully Supported by Xilinx Development System
- Automatic place and route software
- Wide selection of PC and Workstation platforms
- Over 100 3rd-party Alliance interfaces
- Supported by shrink-wrap Foundation software
Description
The XC5200 Field-Programmable Gate Array Family is
engineered to deliver low cost. Building on experiences
gained with three previous successful SRAM FPGA fami-
lies, the XC5200 family brings a robust feature set to pro-
grammable logic design. The VersaBlocklogic module,
the VersaRing I/O interface, and a rich hierarchy of inter-
connect resources combine to enhance design flexibility
and reduce time-to-market. Complete support for the
XC5200 family is delivered through the familiar Xilinx soft-
ware environment. The XC5200 family is fully supported on
popular workstation and PC platforms. Popular design
entry methods are fully supported, including ABEL, sche-
matic capture, VHDL, and Verilog HDL synthesis. Design-
ers utilizing logic synthesis can use their existing tools to
design with the XC5200 devices.
.
Table 1: XC5200 Field-Programmable Gate Array Family Members
Device
Logic Cells
Max Logic Gates
Typical Gate Range
VersaBlock Array
CLBs
Flip-Flops
I/Os
TBUFs per Longline
XC5202
256
3,000
2,000 - 3,000
8x8
64
256
84
10
XC5204
XC5206
XC5210
XC5215
480
784
1,296
1,936
6,000
10,000
16,000
23,000
4,000 - 6,000 6,000 - 10,000 10,000 - 16,000 15,000 - 23,000
10 x 12
14 x 14
18 x 18
22 x 22
120 196 324 484
480
784
1,296
1,936
124 148 196 244
14 16 20 24
7
November 5, 1998 (Version 5.2)
7-83

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