XC40200XV Datasheet PDF - Xilinx
| Part Number | XC40200XV | |
| Description | XC4000XLA/XV Field Programmable Gate Arrays | |
| Manufacturers | Xilinx | |
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Product Obsolete/Under Obsolescence
0
XC4000XLA/XV Field Programmable
R Gate Arrays
DS015 (v2.0) March 1, 2013
0 0* Product Specification
XC4000XLA/XV Family Features
Electrical Features
Note: XC4000XLA devices are improved versions of
XC4000XL devices. The XC4000XV devices have the
same features as XLA devices, incorporate additional inter-
connect resources and extend gate capacity to 500,000
system gates. The XC4000XV devices require a separate
2.5V power supply for internal logic but maintain 5V I/O
compatibility via a separate 3.3V I/O power supply. For
additional information about the XC4000XLA/XV device
architecture, refer to the XC4000E/X FPGA Series general
and functional descriptions.
• System-featured Field-Programmable Gate Arrays
- Select-RAMTM memory: on-chip ultra-fast RAM with
- Synchronous write option
- Dual-port RAM option
- Flexible function generators and abundant flip-flops
- Dedicated high-speed carry logic
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
networks
• Flexible Array Architecture
• Low-power Segmented Routing Architecture
• Systems-oriented Features
- IEEE 1149.1-compatible boundary scan
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- Unlimited reprogrammability
• Read Back Capability
- Program verification and internal node observability
*Table 1: XC4000XLA Series Field Programmable Gate Arrays
• XLA Devices Require 3.0 - 3.6 V (VCC)
• XV Devices Require 2.3- 2.7 V (VCCINT)
and 3.0 - 3.6 V (VCCIO)
• 5.0 V TTL compatible I/O
• 3.3 V LVTTL, LVCMOS compliant I/O
• 5.0 V and 3.0 V PCI Compliant I/O
• 12 mA or 24 mA Current Sink Capability
• Safe under All Power-up Sequences
• XLA Consumes 40% Less Power than XL
• XV Consumes 65% Less Power than XL
• Optional Input Clamping to VCC (XLA) or VCCIO (XV)
Additional Features
• Footprint Compatible with XC4000XL FPGAs - Lower
cost with improved performance and lower power
• Advanced Technology — 5 layer metal, 0.25 μm CMOS
process (XV) or 0.35 μm CMOS process (XLA)
• Highest Performance — System performance beyond
100 MHz
• High Capacity — Up to 500,000 system gates and
270,000 synchronous SRAM bits
• Low Power — 3.3 V/2.5 V technology plus segmented
routing architecture
• Safe and Easy to Use — Interfaces to any combination
of 3.3 V and 5.0 V TTL compatible devices
Device
Logic
Cells
Max Logic Max. RAM
Typical
Gates
Bits
Gate Range
(No RAM) (No Logic) (Logic and RAM)*
XC4013XLA
1,368
13,000
18,432 10,000 - 30,000
XC4020XLA
1,862
20,000
25,088 13,000 - 40,000
XC4028XLA
2,432
28,000
32,768 18,000 - 50,000
XC4036XLA
3,078
36,000
41,472 22,000 - 65,000
XC4044XLA
3,800
44,000
51,200 27,000 - 80,000
XC4052XLA
4,598
52,000
61,952 33,000 - 100,000
XC4062XLA
5,472
62,000
73,728 40,000 - 130,000
XC4085XLA
7,448
85,000 100,352 55,000 - 180,000
XC40110XV
9,728
110,000 131,072 75,000 - 235,000
XC40150XV
12,312
150,000 165,888 100,000 - 300,000
XC40200XV
16,758
200,000 225,792 130,000 - 400,000
XC40250XV
20,102
250,000 270,848 180,000 - 500,000
* Maximum values of gate range assume 20-30% of CLBs used as RAM
CLB
Matrix
24 x 24
28 x 28
32 x 32
36 x 36
40 x 40
44 x 44
48 x 48
56 x 56
64 x 64
72 x 72
84 x 84
92 x 92
Total
CLBs
576
784
1,024
1,296
1,600
1,936
2,304
3,136
4,096
5,184
7,056
8,464
Number
of
Flip-Flops
1,536
2,016
2,560
3,168
3,840
4,576
5,376
7,168
9,216
11,520
15,456
18,400
Max.
User I/O
192
224
256
288
320
352
384
448
448
448
448
448
Required
Configur-
ation Bits
393,632
521,880
668,184
832,528
1,014,928
1,215,368
1,433,864
1,924,992
2,686,136
3,373,448
4,551,056
5,433,888
6
DS015 (v2.0) March 1, 2013 - Product Specification
6-157
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Product Obsolete/Under Obsolescence
R
XC4000XLA/XV Field Programmable Gate Arrays
JTAG Enhancements
XC4000XLA/XV devices have improved JTAG functionality
and performance in the following areas:
• IDCODE - The IDCODE register in JTAG is now
supported. All future Xilinx FPGAs will support the
IDCODE register. By using the IDCODE, the device
connected to the JTAG port can be determined. The
use of the IDCODE enables selective configuration
dependent upon the FPGA found. The IDCODE register
has the following binary format:
vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1
Where:
c = the company code;
a = the array dimension in CLBs;
f = the Family code;
v = the die version number
Family Codes = 01 for XLA;
= 02 for SpartanXL;
= 03 for Virtex;
= 07 for XV.
Xilinx company code = 49 (hex)
Table 4: IDCODEs assigned to XC4000XLA/XV FPGAs
FPGA
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
XC40110XV
XC40150XV
XC40200XV
XC40250XV
IDCODE
0x00218093
0x0021c093
0x00220093
0x00224093
0x00228093
0x0022c093
0x00230093
0x00238093
0x00e40093
0x00e48093
0x00e54093
0x00e5c093
• Configuration State - The configuration state is
available to JTAG controllers.
• Configure Disable - The JTAG port can be prevented
from reconfiguring the FPGA
• TCK Startup - TCK can now be used to clock the
start-up block in addition to other user clocks.
• CCLK holdoff - Changed the requirement for Boundary
Scan Configure or EXTEST to be issued prior to the
release of INIT pin and CCLK cycling.
• Reissue configure - The Boundary Scan Configure
can be reissued to recover from an unfinished attempt
to configure the device.
• Bypass FF - Bypass FF and IOB is modified to provide
DRCLOCK only during BYPASS for the bypass flip-flop
and during EXTEST or SAMPLE/PRELOAD for the IOB
register.
XV and XLA Family Differences
The high density of the XC4000XV family FPGAs is
achieved by using advanced 0.25 micron silicon technol-
ogy. A 2.5 Volt power supply (VCCINT) is necessary to pro-
vide the reduced supply voltage required by 0.25 micron
internal logic, however to maintain TTL compatibility a 3.3V
power supply (VCCIO) is required by the I/O.
To accommodate the higher gate capacity of XV devices,
additional interconnect has been added. These differences
are detailed below.
• VCCINT (2.5 Volt) Power Supply Pins
The XV family of FPGAs requires a 2.5V power supply
for internal logic, which is named VCCINT. The pins
assigned to the VCCINT supply are named in the pinout
guide for the XC4000XV FPGAs and in Table 5 on page
162.
• VCCIO (3.3 Volt) Power Supply Pins
Both the XV and XLA FPGAs use a 3.3V power supply
to power the I/O pins. The I/O supply is named VCCIO
in the XV family.
• Octal-Length Interconnect Channels
The XC40110XV, XC40150XV, XC40200XV, and
XC40250XV have enhanced routing. Eight routing
channels of octal length have been added to each CLB
in both vertical and horizontal dimensions.
XLA-to-XL Socket Compatibility
The XC4000XLA devices are generally available in the
same packages as equivalent XL devices, however the
range of packages available for the XC4085XLA has been
extended to include smaller packages such as the HQ240.
XV-to-XL/XLA Socket Compatibility
XC4000XV devices are available in five package options,
pin-grid PG599 and ball-grid BG560, BG432, and BG352
and quad-flatpack HQ240. With the exception of the
VCCINT power pins, XC4000XV FPGAs are compatible
with XL and XLA devices in these packages if the following
guidelines are followed:
• Lay out the PCB for the XV pinout.
• When an XL or XLA device is installed disconnect the
VCCINT (2.5 V) supply. For the PG599, VCCINT should
be connected to 3.3V. For BG560, BG432 and BG352
and HQ240 packages, the VCCINT voltage source
should be left unconnected. The unused I/O pins in the
XL/XLA devices connected to VCCINT will be pulled up
to 3.3V. Care must be taken to insure that these pins
are not driven when the XL/XLA device is operative.
• When an XC4000XV is installed, the VCCINT pins must
6
DS015 (v2.0) March 1, 2013 - Product Specification
6-161
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