XC4013D Datasheet PDF - Xilinx
| Part Number | XC4013D | |
| Description | Logic Cell Array Family | |
| Manufacturers | Xilinx | |
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® XC4000, XC4000A, XC4000H
Logic Cell Array Families
Product Description
Features
Description
• Third Generation Field-Programmable Gate Arrays
– Abundant flip-flops
– Flexible function generators
– On-chip ultra-fast RAM
The XC4000 families of Field-Programmable Gate Arrays
(FPGAs) provide the benefits of custom CMOS VLSI, while
avoiding the initial cost, time delay, and inherent risk of a
conventional masked gate array.
– Dedicated high-speed carry-propagation circuit
– Wide edge decoders
The XC4000 families provide a regular, flexible, program-
mable architecture of Configurable Logic Blocks (CLBs),
– Hierarchy of interconnect lines
interconnected by a powerful hierarchy of versatile routing
– Internal 3-state bus capability
resources, and surrounded by a perimeter of program-
– Eight global low-skew clock or signal distribution
mable Input/Output Blocks (IOBs).
network
• Flexible Array Architecture
XC4000-family devices have generous routing resources to
accommodate the most complex interconnect patterns.
– Programmable logic blocks and I/O blocks
XC4000A devices have reduced sets of routing resources,
– Programmable interconnects and wide decoders
sufficient for their smaller size. XC4000H high I/O devices
• Sub-micron CMOS Process
– High-speed logic and Interconnect
maintain the same routing resources and CLB structure as
the XC4000 family, while nearly doubling the available I/O.
– Low power consumption
The devices are customized by loading configuration data
• Systems-Oriented Features
– IEEE 1149.1-compatible boundary-scan logic support
– Programmable output slew rate
– Programmable input pull-up or pull-down resistors
into the internal memory cells. The FPGA can either actively
read its configuration data out of external serial or byte-
parallel PROM (master modes), or the configuration data
can be written into the FPGA (slave and peripheral modes).
– 12-mA sink current per output (XC4000 family)
The XC4000 families are supported by powerful and so-
– 24-mA sink current per output (XC4000A and
phisticated software, covering every aspect of design: from
XC4000H families)
schematic entry, to simulation, to automatic block place-
• Configured by Loading Binary File
– Unlimited reprogrammability
ment and routing of interconnects, and finally the creation
of the configuration bit stream.
– Six programming modes
Since Xilinx FPGAs can be reprogrammed an unlimited
• XACT Development System runs on ’386/’486-type PC,
NEC PC, Apollo, Sun-4, and Hewlett-Packard 700
series
– Interfaces to popular design environments like
Viewlogic, Mentor Graphics and OrCAD
– Fully automatic partitioning, placement and routing
number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hard-
ware must be adapted to different user applications. FPGAs
are ideal for shortening the design and development cycle,
but they also offer a cost-effective solution for production
rates well beyond 1000 systems per month.
– Interactive design editor for design optimization
– 288 macros, 34 hard macros, RAM/ROM compiler
Table 1. The XC4000 Families of Field-Programmable Gate Arrays
Device
XC4002A 4003/3A 4003H 4004A 4005/5A 4005H 4006 4008 4010/10D 4013/13D 4020 4025
Appr. Gate Count
CLB Matrix
Number of CLBs
Number of Flip-Flops
Max Decode Inputs
(per side)
Max RAM Bits
Number of IOBs
2,000
8x8
64
256
24
2,048
64
3,000
10 x 10
100
360
30
3,000
10 x 10
100
200
30
4,000
12 x 12
144
480
36
5,000
14 x 14
196
616
42
5,000 6,000
14 x 14 16 x 16
196 256
392 768
42 48
8,000
18 x 18
324
936
54
10,000
20 x 20
400
1,120
60
13,000
24 x 24
576
1,536
72
20,000
28 x 28
784
2,016
84
25,000
32 x 32
1,024
2,560
96
3,200 3,200 4,608 6,272 6,272 8,192 10,368 12,800* 18,432* 25,088 32,768
80 160 96 112 192 128 144 160 192 224 256
*XC4010D and XC4013D have no RAM
2-7
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Speed Is Enhanced Two Ways
Delays in LCA-based designs are layout dependent. While
this makes it hard to predict a worst-case guaranteed
performance, there is a rule of thumb designers can
consider — the system clock rate should not exceed one
third to one half of the specified toggle rate. Critical
portions of a design, shift registers and simple counters,
can run faster — approximately two thirds of the specified
toggle rate.
The XC4000 family can run at synchronous system clock
rates of up to 60 MHz. This increase in performance over
the previous families stems from two basic improve-
ments: improved architecture and more abundant routing
resources.
Improved Architecture
More Inputs: The versatility of the CLB function genera-
tors improves system speed significantly. Table 3 shows
how the XC4000 families implement many functions more
efficiently and faster than is possible with XC3000 devices.
A 9-bit parity checker, for example, can be implemented in
one CLB with a propagation delay of 7 ns. Using a
XC3000-family device, the same function requires two
CLBs with a propagation delay of 2 x 5.5 ns = 11 ns. One
XC4000 CLB can determine whether two 4-bit words are
identical, again with a 7-ns propagation delay. The ninth
input can be used for simple ripple expansion of this
identity comparator (25.5 ns over 16 bits, 51.5 ns over
32 bits), or a 2-layer identity comparator can generate the
result of a 32-bit comparison in 15 ns, at the cost of a single
extra CLB. Simpler functions like multiplexers also benefit
from the greater flexibility of the XC4000-families CLB. A
16-input multiplexer uses 5 CLBs and has a delay of only
13.5 ns.
More Outputs: The CLB can pass the combinatorial
output(s) to the interconnect network, but can also store
the combinatorial result(s) or other incoming data in one or
two flip-flops, and connect their outputs to the interconnect
network as well. With XC3000-families CLBs the designer
has to make a choice, either output the combinatorial
function or the stored value. In the XC4000 families, the flip
flops can be used as registers or shift registers without
blocking the function generators from performing a differ-
ent, perhaps unrelated task. This increases the functional
density of the devices.
When a function generator drives a flip-flop in a CLB, the
combinatorial propagation delay overlaps completely with
the set-up time of the flip-flop. The set-up time is specified
between the function generator inputs and the clock input.
This represents a performance advantage over competing
technologies where combinatorial delays must be added
to the flip-flop set-up time.
Fast Carry: As described earlier, each CLB includes high-
speed carry logic that can be activated by configuration.
The two 4-input function generators can be configured as
a 2-bit adder with built-in hidden carry that can be ex-
panded to any length. This dedicated carry circuitry is so
fast and efficient that conventional speed-up methods like
carry generate/propagate are meaningless even at the
16-bit level, and of marginal benefit at the 32-bit level.
A 16-bit adder requires nine CLBs and has a combinatorial
carry delay of 20.5 ns. Compare that to the 30 CLBs and
50 ns, or 41 CLBs and 30 ns in the XC3000 family.
The fast-carry logic opens the door to many new applica-
tions involving arithmetic operation, where the previous
generations of FPGAs were not fast and/or not efficient
enough. High-speed address offset calculations in micro-
processor or graphics systems, and high-speed addition in
digital signal processing are two typical applications.
Faster and More Efficient Counters: The XC4000-fami-
lies fast-carry logic puts two counter bits into each CLB and
runs them at a clock rate of up to 42 MHz for 16 bits,
whether the counters are loadable or not. For a 16-bit
Table 3. Density and Performance for Several Common Circuit Functions
16-bit Decoder From Input Pad
24-bit Accumulator
State Machine Benchmark*
16:1 Multiplexer
16-bit Unidirectional
Loadable Counter
16-bit U/D Counter
16-bit Adder
* 16 states, 40 transitions, 10 inputs, 8 outputs
Max Density
Max Speed
Max Density
Max Speed
Max Density
Max Speed
XC3000 (-125)
15 ns
17 MHz
18 MHz
16 ns
20 MHz
34 MHz
20 MHz
30 MHz
50 ns
30 ns
4 CLBs
46 CLBs
34 CLBs
8 CLBs
16 CLBs
23 CLBs
16 CLBs
27 CLBs
30 CLBs
41 CLBs
XC4000 (-5)
12 ns
32 MHz
30 MHz
16 ns
40 MHz
42 MHz
40 MHz
40 MHz
20.5 ns
20.5 ns
0 CLBs
13 CLBs
26 CLBs
5 CLBs
8 CLBs
9 CLBs
8 CLBs
8 CLBs
9 CLBs
9 CLBs
2-11
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| Information | Total 30 Pages | |
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