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PDF XC1800 Data sheet ( Hoja de datos )
| Número de pieza | XC1800 | |
| Descripción | XC1800 Series of In-System Programmable Configuration PROMs | |
| Fabricantes | Xilinx | |
| Logotipo |  |
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®
September 17, 1999 (Version 1.3)
0
XC1800 Series of In-System
Programmable Configuration
PROMs
0 6* Preliminary Product Specification
Features
• In-system programmable 3.3V PROMs for configuration
of Xilinx FPGAs
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• IEEE Std 1149.1 boundary-scan (JTAG) support
• Simple interface to the FPGA; could be configured to
use only one user I/O pin
• Cascadable for storing longer or multiple bitstreams
• Dual configuration modes
- Serial Slow/Fast configuration (up to 15 mHz).
- Parallel
• Low-power advanced CMOS FLASH process
• 5 V tolerant I/O pins accept 5 V, 3.3 V and 2.5 V signals.
• 3.3 V or 2.5 V output capability
• Available in PC20, SO20, PC44 and VQ44 packages.
• Design support using the Xilinx Alliance and
Foundation series software packages.
• JTAG command initiation of standard FPGA
configuration.
Description
Xilinx introduces the XC1800 series of in-system program-
mable configuration PROMs. Initial devices in this 3.3V
family are a 4 megabit, a 2 megabit, a 1 megabit, a 512
Kbit, a 256 Kbit, and a 128 Kbit PROM that provide an
easy-to-use, cost-effective method for re-programming and
storing large Xilinx FPGA or CPLD configuration bit-
streams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising CCLK, data is available on the PROM
DATA (D0) pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. When the FPGA is in Slave
Serial mode, the PROM and the FPGA are clocked by an
external clock.
When the FPGA is in Express or SelectMAP Mode, an
external oscillator will generate the configuration clock that
drives the PROM and the FPGA. After the rising CCLK
edge, data are available on the PROM’s DATA (D0-D7)
pins. The data will be clocked into the FPGA on the follow-
ing rising edge of the CCLK. Neither Express nor Select-
MAP utilize a Length Count, so a free-running oscillator
may be used. See Figure 5
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family or with
the XC1700L one-time programmable Serial PROM family.
CLK CE
OE/Reset
TCK
TMS
TDI
TDO
Control
and
JTAG
Interface
Data
Address
Memory
Data
Serial
or
Parallel
Interface
CF
Figure 1: XC1800 Series Block Diagram
September 17, 1999 (Version 1.3)
CEO
D0 DATA
(Serial or Parallel
(Express/SelectMAP) Mode)
D1 - D7
Express Mode and
SelectMAP Interface
99020300
1
1 page  
R
XC1800 Series of In-System Programmable Configuration PROMs
In-System Programming
One or more in-system programmable PROMs can be
daisy chained together and programmed in-system via the
standard 4-pin JTAG protocol as shown in Figure 2. In-sys-
tem programming offers quick and efficient design itera-
tions and eliminates unnecessary package handling or
socketing of devices. The Xilinx development system pro-
vides the programming data sequence using Xilinx JTAG
Programmer software and a download cable, a third-party
JTAG development system, a JTAG-compatible board
tester, or a simple microprocessor interface that emulates
the JTAG instruction sequence.
All outputs are 3-stated or held at clamp levels during in-
system programming.
External Programming
Xilinx reprogrammable PROMs can also be programmed
by the Xilinx HW-130 device programmer. This provides the
added flexibility of using pre-programmed devices in
design, boundary-scan manufacturing tools, with an in-sys-
tem programmable option for future enhancements and
design changes.
Reliability and Endurance
Xilinx in-system programmable products provide a mini-
mum endurance level of 10,000 in-system program/erase
cycles and a minimum data retention of 10 years. Each
device meets all functional, performance, and data reten-
tion specifications within this endurance limit.
Design Security
The Xilinx in-system programmable PROM devices incor-
porate advanced data security features to fully protect the
programming data against unauthorized reading. Table 2
shows the security setting available.
The read security bit can be set by the user to prevent the
internal programming pattern from being read or copied via
JTAG. When set it allows device erase. Erasing the entire
device is the only way to reset the read security bit.
Table 2: Data Security Options
Default
Read Allowed
Program/Erase Allowed
Set
Read Inhibited via JTAG
Erase Allowed
V CC
GND
(a) (b) X5902
Figure 2: In-System Programming Operation (a) solder device to PCB and (b) Program using Download Cable
September 17, 1999 (Version 1.3)
5
5 Page 
R
XC1800 Series of In-System Programmable Configuration PROMs
5V Tolerant I/Os
The I/Os on each re-programmable PROM are fully 5V tol-
erant even through the core power supply is 3.3 volts. This
allows 5V CMOS signals to connect directly to the PROM
inputs without damage. In addition, the 3.3V VCC power
supply can be applied before or after 5V signals are applied
to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins,
the core power supply (VCC), and the output power supply
(VCCO) may have power applied in any order. This makes
the PROM devices immune to power supply sequencing
issues.
Reset Activation
On power up, OE/RESET is held low until the XC1800 is
active (1ms) and able to supply data after receiving a CCLK
Table 6: Truth Table for PROM Control Inputs
pulse from the FPGA. OE/RESET is connected to an exter-
nal resistor to pull OE/RESET HIGH releasing the FPGA
INIT and allowing configuration to begin. OE/RESET is
held low until the XC1800 voltage reaches the operating
voltage range. If the power drops below 2.0 Volts, the
PROM will reset.
Standby Mode
The PROM enters a low-power standby mode whenever
CE is asserted High. The output remains in a high imped-
ance state regardless of the state of the OE input. JTAG
pins TMS, TDI and TDO can be 3-state or high.
Control Inputs
OE/RESET
CE
Internal Address
DATA
Low
High
Low
Low
Low
High
if address < TC: increment
if address > TC: don’t change
Held reset
Held reset
active
3-state
3-state
3-state
High
High
Held reset
3-state
Note: TC = Terminal Count = highest address value. TC+1 = address 0.
Outputs
CEO
High
Low
High
High
High
Icc
active
reduced
active
standby
standby
September 17, 1999 (Version 1.3)
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet XC1800.PDF ] | |
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