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PDF X9400 Data sheet ( Hoja de datos )
| Número de pieza | X9400 | |
| Descripción | Quad Digitally Controlled Potentiometers (XDCP) | |
| Fabricantes | Xicor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de X9400 (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
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APPLICATION NOTES
AVAILABLE
AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135
Low Noise/Low Power/SPI Bus
X9400
Quad Digitally Controlled Potentiometers (XDCP™)
FEATURES
• Four potentiometers per package
• 64 resistor taps
• SPI serial interface for write, read, and transfer
operations of the potentiometer
• Wiper resistance, 40Ω typical at 5V.
• Four non-volatile data registers for each
potentiometer
• Non-volatile storage of multiple wiper position
• Power on recall. Loads saved wiper position on
power up.
• Standby current < 1µA max
• System VCC: 2.7V to 5.5V operation
• Analog V+/V–: -5V to +5V
• 10KΩ, 2.5KΩ End to end resistance
• 100 yr. data retention
• Endurance: 100,000 data changes per bit per
register
• Low power CMOS
• 24-lead SOIC, 24-lead TSSOP, and 24-lead XBGA
packages
DESCRIPTION
The X9400 integrates four digitally controlled
potentiometers (XDCPs) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI
serial bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and four nonvolatile Data Registers (DR0-3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array through the switches.
Power up recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC
VSS
V+
V-
HOLD
CS
SCK
SO
SI
A0
A1
WP
Interface
and
Control
Circuitry
8
Data
Pot 0
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
VH0/RH0
VL0/RL0
VW0/RW0
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 2
VH2/RH2
VL2/RL2
VW2/RW2
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
VW1/RW1
Resistor
Array
Pot 1
VH1/RH1
VL1/RL1
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
VW3/RW3
Resistor
Array
Pot 3
VH3/RH3
VL3/RL3
REV 1.1.4 10/11/02
www.xicor.com
Characteristics subject to change without notice. 1 of 22
1 page  
X9400
Figure 3. Instruction Byte Format
Register
Select
I3 I2 I1 I0 R1 R0 P1 P0
Instructions
Pot Select
The four high order bits of the instruction byte specify
the operation. The next two bits (R1 and R0) select one
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last two bits
(P1 and P0) selects which one of the four
potentiometers is to be affected by the instruction.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte. These
instructions are:
– XFR Data Register to Wiper Counter Register—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
– XFR Wiper Counter Register to Data Register —This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
– Global XFR Data Register to Wiper Counter Register —
This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.
– Global XFR Wiper Counter Register to Data Register —
This transfers the contents of all Wiper Counter
Registers to the specified associated Data Registers.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper
to this action will be delayed by tWRL. A transfer from
the WCR (current wiper position), to a data register is a
write to nonvolatile memory and takes a minimum of
tWR to complete. The transfer can occur between one of
the four potentiometers and one of its associated
registers; or it may occur globally, where the transfer
occurs between all potentiometers and one associated
register.
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9400; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:
– Read Wiper Counter Register—read the current
wiper position of the selected pot,
– Write Wiper Counter Register—change current wiper
position of the selected pot,
– Read Data Register—read the contents of the
selected data register;
– Write Data Register—write a new value to the
selected data register.
– Read Status—This command returns the contents of
the WIP bit which indicates if the internal write cycle
is in progress.
The sequence of these operations is shown in Figure 5
and Figure 6.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length is
indeterminate. Once the command is issued, the master
can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
capability to the host. For each SCK clock pulse (tHIGH)
while SI is HIGH, the selected wiper will move one
resistor segment towards the VH/RH terminal. Similarly,
for each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the VL/RL
terminal. A detailed illustration of the sequence and
timing for this operation are shown in Figure 7 and Figure
8.
REV 1.1.4 10/11/02
www.xicor.com
Characteristics subject to change without notice. 5 of 22
5 Page 
X9400
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Symbol
ICC1
ICC2
ISB
ILI
ILO
VIH
VIL
VOL
Parameter
VCC supply current (Active)
VCC supply current (Nonvol-
atile Write)
VCC current (standby)
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
Min.
VCC x 0.7
–0.5
Limits
Typ. Max.
400
Units
µA
1 mA
1
10
10
VCC + 0.5
VCC x 0.1
0.4
µA
µA
µA
V
V
V
Test Conditions
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
SCK = SI = VSS, Addr. = VSS
VIN = VSS to VCC
VOUT = VSS to VCC
IOL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
years
CAPACITANCE
Symbol
COUT(4)
CIN(4)
Test
Output capacitance (SO)
Input capacitance (A0, A1, SI, and SCK)
POWER-UP TIMING
Symbol
tPUR(5)
tPUW(5)
tR VCC(4)
Parameter
Power-up to initiation of read operation
Power-up to initiation of write operation
VCC Power up ramp
Max.
8
6
Min.
0.2
Unit
pF
pF
Test Conditions
VOUT = 0V
VIN = 0V
Max.
1
5
50
Unit
ms
ms
V/msec
POWER UP REQUIREMENTS (Power Up sequencing
can affect correct recall of the wiper registers)
EQUIVALENT A.C. LOAD CIRCUIT
The preferred power-on sequence is as follows: First
VCC, then the potentiometer pins, RH, RL, and RW.
Voltage should not be applied to the potentiometer pins
before V+ or V- is applied. The VCC ramp rate specifi-
cation should be met, and any glitches or slope
changes in the VCC line should be held to <100mV if
possible. If VCC powers down, it should be held below
0.1V for more than 1 second before powering up again
in order for proper wiper register recall. Also, VCC
should not reverse polarity by more than 0.5V. Recall of
wiper position will not be complete until VCC, V+ and V-
reach their final value.
SDA Output
5V
1533Ω
100pF
REV 1.1.4 10/11/02
www.xicor.com
Characteristics subject to change without notice. 11 of 22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet X9400.PDF ] | |
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