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PDF X9279 Data sheet ( Hoja de datos )
| Número de pieza | X9279 | |
| Descripción | Single Digitally-Controlled (XDCP) Potentiometer | |
| Fabricantes | Xicor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de X9279 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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APPLICATION NOTES AND DEVELOPMENT SYSTEM
AVAILABLE
AN99 • AN115 • AN124 •AN133 • AN134 • AN135
Single Supply / Low Power / 256-tap / 2-Wire Bus
X9279
Single Digitally-Controlled (XDCPTM) Potentiometer
FEATURES
• 256 Resistor Taps
• 2-Wire Serial Interface for write, read, and
transfer operations of the potentiometer
• Wiper Resistance, 100Ω typical @ 5V
• 16 Nonvolatile Data Registers for Each
Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on
Power Up.
• Standby Current < 5µA Max
• VCC: 2.7V to 5.5V Operation
• 50KΩ, 100KΩ versions of End to End Resistance
• Endurance: 100,000 Data Changes per Bit per
Register
• 100 yr. Data Retention
• 14-Lead TSSOP, 16-Lead CSP (Chip Scale
Package)
• Low Power CMOS
DESCRIPTION
The X9279 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-Wire
bus interface. The potentiometer has associated with it
a volatile Wiper Counter Register (WCR) and a four
nonvolatile Data Registers that can be directly written
to and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
though the switches. Powerup recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
VCC
2-Wire
Bus
Interface
Address
Data
Status
Bus
Interface
and Control
Write
Read
Transfer
Inc/Dec
Control
Power On Recall
Wiper Counter
Register (WCR)
Data Registers
16 Bytes
RH
wiper
50KΩ and 100KΩ
256-taps
POT
VSS
RW RL
REV 1.1.7 2/6/03
www.xicor.com
Characteristics subject to change without notice. 1 of 24
1 page  
X9279
PRINCIPLES OF OPERATION
The X9279 is a integrated microcircuit incorporating a
resistor array and associated registers and counter
and the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometers. This section provides detail
description of the following:
– Resistor Array Description.
– Serial Interface Description.
– Instruction and Register Description.
Array Description
The X9279 is comprised of a resistor array (see Figure
1). The array contains, in effect, 255 discrete resistive
segments that are connected in series. The physical
ends of each array are equivalent to the fixed terminals
of a mechanical potentiometer (RH and RL inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(RW) output. Within each individual array only one
switch may be turned on at a time.
Figure 1. Detailed Potentiometer Block Diagram
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256 switches
(see Table 1).
The WCR may be written directly. These Data
Registers can the WCR can be read and written by the
host system.
Power Up and Down Recommendations.
There are no restrictions on the power-up or power-
down conditions of VCC and the voltages applied to the
potentiometer pins provided that VCC is always more
positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH,
VL, VW. The VCC ramp rate specification is always in
effect.
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0
(DR0)
REGISTER 1
(DR1)
88
BANK_0 Only
REGISTER 2
(DR2)
REGISTER 3
(DR3)
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR)
IF WCR = 00[H] THEN RW = RL
IF WCR = FF[H] THEN RW = RH
UP/DN
MODIFIED SCK
INC/DEC
LOGIC
UP/DN
CLK
C
O
U
N
T
E
R
D
E
C
O
D
E
RH
RL
RW
REV 1.1.7 2/6/03
www.xicor.com
Characteristics subject to change without notice. 5 of 24
5 Page 
X9279
Figure 4. Three-Byte Instruction Sequence
SCL
SDA
0 1 0 10
S ID3 ID2 ID1 ID0 0 A2 A1 A0 A I3 I2 I1 I0 RB RA P1 P0 A D7 D6 D5 D4 D3 D2 D1 D0 A S
T C C CT
A
R Device ID
External K
Instruction
Register Pot/BankK
WCR[7:0] valid only when P1=P0=0; K
O
P
T
Address
Opcode
Address Address
or
Data Register D[7:0] for all values of P1 and P0
Figure 5. Increment/Decrement Instruction Squence
SCL
SDA
0101 0
S ID3 ID2 ID1 ID0
T
A Device ID
R
T
0 A2 A1 A0
External
Address
A I3 I2 I1 I0 RB RA P1 P0 A I I
C
K
Instruction
CN N
Register Pot/Bank K
C
1
C
2
Opcode
Address Address
ID
NE
CC
n1
DS
ET
CO
nP
Figure 6. Increment/Decrement Timing Limits
INC/DEC
CMD
Issued
SCL
tWRID
SDA
VW/RW
Voltage Out
REV 1.1.7 2/6/03
www.xicor.com
Characteristics subject to change without notice. 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet X9279.PDF ] | |
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