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PDF X9119 Data sheet ( Hoja de datos )
| Número de pieza | X9119 | |
| Descripción | Single Digitally-Controlled Potentiometer | |
| Fabricantes | Xicor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de X9119 (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
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APPLICATION NOTES AND DEVELOPMENT SYSTEM
AVAILABLE
AN99 • AN115 • AN124 •AN133 • AN134 • AN135
Single Supply / Low Power / 1024-tap / 2-Wire bus
Preliminary Information
X9119
Single Digitally-Controlled (XDCP™) Potentiometer
FEATURES
• 1024 Resistor Taps – 10-Bit Resolution
• 2-Wire Serial Interface for write, read, and
transfer operations of the potentiometer
• Wiper Resistance, 40Ω Typical @ VCC = 5V
• Four Non-Volatile Data Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on
Power Up.
• Standby Current < 3µA Max
• VCC: 2.7V to 5.5V Operation
• 100KΩ End to End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes Per Bit Per
Register
• 14-Lead TSSOP, 15-Lead XBGA
• Low Power CMOS
• Single Supply version of the X9118
DESCRIPTION
The X9119 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digital controlled potentiometer is implemented
using 1023 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-wire bus interface. The potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and a
four non-volatile Data Registers that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array though the switches. Powerup recalls the
contents of the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
VCC
RH
2-Wire
Bus
Interface
Address
Data
Status
Bus
Interface &
Control
Write
Read
Transfer
Control
Power On Recall
Wiper Counter
Register (WCR)
Data Registers
(DR0-DR3)
Wiper
100KΩ
1024-taps
POT
VSS NC NC
RW RL
REV 1.1.11 3/12/02
www.xicor.com
Characteristics subject to change without notice. 1 of 22
1 page  
X9119 – Preliminary Information
Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path
From Interface
Circuitry
Register 0
(DR0)
10
Register 2
(DR2)
If WCR = 000[HEX] then RW = RL
If WCR = 3FF[HEX] then RW = RH
Register 1
(DR1)
10
Register 3
(DR3)
Serial
Bus
Input
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
C
O
U
N
T
E
R
D
E
C
O
D
E
RH
RL
RW
Serial Interface Description
SERIAL INTERFACE
The X9119 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9119 will be considered a
slave device in all applications.
CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 3.
START CONDITION
All commands to the X9119 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9119 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is met.
See Figure 3.
STOP CONDITION
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 3.
ACKNOWLEDGE
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9119 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9119 will respond with a final acknowledge.
See Figure 2.
REV 1.1.11 3/12/02
www.xicor.com
Characteristics subject to change without notice. 5 of 22
5 Page 
X9119 – Preliminary Information
Write Data Register (DR)
Device Type Device
S Identifier
Addresses
T
A
R
T
0
1
0
1 A2 A1 A0
Instruction Register
Wiper Position or Data
Wiper Position or Data
Opcode Addresses
(Sent by Master on SDA)
(Sent by Master on SDA)
S S S SS
A
C
K
1
1
0
0 RB RA
0
0
A
C
K
X
X
X
X
X
WW
X
C
R
C
R
A
C
K
W
C
R
W
C
R
W
C
R
W
C
R
W
C
R
W
C
R
W
C
R
W
C
R
A
C
K
T
O
P
98
76543210
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device Type
Device
S Identifier
Addresses
T
A
R
T
0
1
0
1 A2 A1 A0
Instruction
Register
S Opcode
Addresses S S
A AT
C CO
K 1 1 1 0 RB RA 0 0 K P
HIGH-VOLTAGE
WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type
Device
S Identifier
Addresses
T
A
R
T
0
1
0
1 A2 A1 A0
Instruction
Register
S Opcode
Addresses S S
A AT
C CO
K 1 1 0 0 RB RA 0 0 K P
Notes: (1) “A2 ~ A0”: stand for the device addresses sent by the master.
(2) WCRx refers to wiper position data in the Wiper Counter Register
REV 1.1.11 3/12/02
www.xicor.com
Characteristics subject to change without notice. 11 of 22
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet X9119.PDF ] | |
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