|
|
PDF X88C64 Data sheet ( Hoja de datos )
| Número de pieza | X88C64 | |
| Descripción | E2 Micro-Peripheral | |
| Fabricantes | Xicor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de X88C64 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
|
No Preview Available !
APPLICATION NOTE
AVA I L A B L E
AN63
8X08581CM64icrocontroller Family Compatible
SLIC
64K
X88C64
E2 Micro-Peripheral
8192 x 8 Bit
FEATURES
• CONCURRENT READ WRITE™
—Dual Plane Architecture
—Isolates Read/Write Functions
Between Planes
—Allows Continuous Execution of Code
From One Plane While Writing in
the Other Plane
• Multiplexed Address/Data Bus
—Direct Interface to Popular 8051 Family
• High Performance CMOS
—Fast Access Time, 120ns
—Low Power
—60mA Active Maximum
—500µA Standby Maximum
• Software Data Protection
• Block Protect Register
—Individually Set Write Lock Out in 1K Blocks
• Toggle Bit Polling
—Early End of Write Detection
• Page Mode Write
—Allows up to 32 Bytes to be Written in
One Write Cycle
• High Reliability
—Endurance: 100,000 Write Cycle
—Data Retention: 100 Years
DESCRIPTION
The X88C64 is an 8K x 8 E2PROM fabricated with
advanced CMOS Textured Poly Floating Gate Tech-
nology. The X88C64 features a Multiplexed Address
and Data bus allowing a direct interface to a variety of
popular single-chip microcontrollers operating in ex-
panded multiplexed mode without the need for addi-
tional interface circuitry.
The X88C64 is internally configured as two indepen-
dent 4K x 8 memory arrays. This feature provides the
ability to perform nonvolatile memory updates in one
array and continue operation out of code stored in the
other array; effectively eliminating the need for an
auxiliary memory device for code storage.
To write to the X88C64, a three-byte command
sequence must precede the byte(s) being written. The
X88C64 also provides a second generation software
data protection scheme called Block Protect. Block
Protect can provide write lockout of the entire device
or selected 1K blocks. There are eight 1K x 8 blocks
that can be write protected individually in any combi-
nation required by the user. Block Protect, in addition
to Write Control input, allows the different segments
of the memory to have varying degrees of alterability
in normal system operation.
FUNCTIONAL DIAGRAM
CE
WR
RD
PSEN
A8–A11
ALE
CONTROL
LOGIC
LX
AD
TE
CC
HO
ED
SE
WC
A12
SOFTWARE
DATA
PROTECT
A12
1K BYTES A12 1K BYTES
M
1K BYTES
1K BYTES
U
1K BYTES X 1K BYTES
1K BYTES
1K BYTES
Y DECODE
CONCURRENT READ WRITE™ is a trademark of Xicor, Inc.
© Xicor, Inc. 1994, 1995, 1996 Patents Pending
3867-1.5 7/9/96 T0/C2/D0 NS
I/O & ADDRESS LATCHES AND BUFFERS
A/D0–A/D7
3867 FHD F02
1 Characteristics subject to change without notice
1 page  
X88C64
PAGE WRITE OPERATION
Regardless of the microcontroller employed, the X88C64
supports page mode write operations. This allows the
microcontroller to write from one to thirty-two bytes of
data to the X88C64. Each individual write within a page
write operation must conform to the byte write timing
requirements. The falling edge of WR starts a timer
delaying the internal programming cycle 100µs. There-
fore, each successive write operation must begin within
100µs of the last byte written. The following waveforms
illustrate the sequence and timing requirements.
Page Write Timing Sequence for WR Controlled Operation
OPERATION
BYTE 0
BYTE 1
BYTE 2
LAST BYTE
READ (1)(2)
AFTER tWC READY FOR
NEXT WRITE OPERATION
CE
ALE
A/D0–A/D7
AIN DIN
AIN DIN
AIN DIN
AIN DIN
AIN DOUT
AIN
AIN
A8–A12
A12=n
A12=n
A12=n
A12=n
A12=x
ADDR
Next Address
WR
PSEN(RD)
tBLC
tWC
3867 FHD F08
Notes: (1) For each successive write within a page write cycle A5–A12 must be the same.
(2) Although it is not illustrated, the microcontroller may interleave read operations between the individual byte writes within the page
write operation. Two responses are possible:
a. Reading from the same plane being written (A12 of Read = A12 of Write) is effectively a Toggle Bit Polling operation.
b. Reading from the opposite plane being written (A12 of Read ≠ A12 of Write) true data will be returned, facilitating the use of a
single memory component as both program and data storage.
5
5 Page 
X88C64
WR Controlled Write Cycle
Symbol
Parameter
tLHLL
tAVLL
tLLAX
tDVWH
tWHDX
tELLL
tWLWH
tWRS
tWRH
tBLC
tWC (7)
ALE Pulse Width
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Chip Enable Setup Time
WR Pulse Width
WR Setup Time
WR Hold Time
Byte Load Time (Page Write)
Write Cycle Time
WR Controlled Write Timing Diagram
Min.
80
20
30
50
30
7
120
30
20
0.5
Max.
100
5
CE
ALE
A/D0–A/D7
A8–A12
WR
tLHLL
tELLL
tAVLL
AIN
tLLAX
tWRS
tWRH
tWRH
tWLWH
DIN
tDVWH
tWHDX
ADDRESS
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
3867 PGM T11
3867 FHD F07
Note: (7) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet X88C64.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| X88C64 | E2 Micro-Peripheral | Xicor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |