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PDF ZL10311 Data sheet ( Hoja de datos )
| Número de pieza | ZL10311 | |
| Descripción | Digital Television DVB-T-On-a-Chip Processor | |
| Fabricantes | Zarlink Semiconductor Inc | |
| Logotipo |  |
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Features
• DTV-SoC for Digital Terrestrial Television (DTT)
• On-chip DVB-T COFDM demodulator with FEC.
• 6 Video DACs on-chip, for Composite or
Component (RGB or Y U/V) Analog Video
• Twin PAL/NTSC DENCs
• Low Power (<1.4W Typical)
• Low Component Count
• Unified SDRAM controller
• I2S Digital Audio Input
• I2S and S/PDIF Digital Audio outputs
• MPEG-2 Audio & Video decoders
• PowerPC 405TM CPU Core with 16k/16k cache,
Memory manager and Virtual memory system
• Complete Linux-based Software Development Kit
(SDK)
• IDE interface
• Inputs for external MPEG-2 Transport Streams,
allowing support for external demodulators (e.g.
Cable TV, Satellite TV)
• Conditional Access (CA) DVB-descrambler
ZL10310/ZL10311
Digital Television DVB-T-On-a-Chip
Processor
Data Sheet
Issue 1.0
November 2002
Ordering Information
ZL10310/GAC 388 ball EPBGA
ZL10311/GAC 388 ball EPBGA
00C to +700C
• Smart Card Interface
• Infrared & UART interface
• DVB-compatible Common Interface (CI) control
and bitstream interfaces
• Multi-stream multiplexing to support internal and
external demodulators
• External Modem support interface
• Supports MacrovisionTM Copy Protection -
(ZL10311 only; available to Macrovision license
holders only)
• Dolby Digital* Decoding - (ZL10311 only;
available to Dolby Digital* license holders only -
*awaiting certification)
De-mod
/JTAG
ADC IN
/De-mod
AGC B
Flash
IDE
CI Control
Smart Card
CODEC/modem
I2C
UART/IRDA
BIT I/O
Bitstream
O/P
/Second Bitstream
Smart Card I/P
ZL10310 / ZL10311 DTV-SOC
EXTIN
JTAG
Bitstream
Multiplexing &
Control
De-
scrambler
ADCIN
COFDM
DeModulator
& FEC
AUX Bus
Cached
PowerPCR 405
Sub System
Peripherals
Power Management
8k Boot
ROM
SDRAM
Controller
SDRAM
Controller
Audio
Decoder
System
DeMultiplex
I 2S
Stereo Audio
DAC
S/PDIF
Video
Decoder
Video Scaler
/ Blender
Comp
Video Video
DENCs
/DACs
Y+U/V
RGB
Analog
Video
SDRAM 1
BUS
SDRAM 0
BUS
(optional)
Figure 1 - Block Diagram of ZL10310 and ZL10311
1
1 page  
Data Sheet
ZL10310/ZL10311
InfraRed Sensor
Terrestrial
Tuner
A
D
C
Tuner Control
ADCIN
AGC B
20.48MHz ADCCLK
Analog Video
Comp Video
RGB or Y U/V
ZL10310
DTV-SOC
Digital Audio
(I2S)
D
A
C
Analog Audio
Serial
EEPROM
Common
Interface
Bitstream o/ps
Bitstream i/ps
COFDM
Clock
CLK
27IN
20.48MHz
Crystal
Oscillator
27MHz
VCXO
Aux
Bus
SDRAM1
Bus
Aux Bus
8MB
FLASH
SDRAM
External
Peripherals
Figure 2 - Block diagram of a typical ZL10310-based Free to Air TV Adaptor
3.0 Typical Digital Television (DTV) Receiver
Figure 2 shows a typical Free to Air TV receiver block diagram employing a ZL10310 DTV-SoC device. In its
minimal configuration, the ZL10310 DTV-SoC device only requires a single 64 Mbit SDRAM, an audio DAC, and a
Flash ROM, which are in addition to a DVB-T tuner front end and a 10-bit analog to digital converter.
The Terrestrial Tuner section performs an independent down conversion of the received DVB-T signal from the
Antenna, to an IF frequency in the range of 30MHz to 57MHz, dependent on television system (typically 36.17MHz
Center Frequency, with ±4MHz span). The analogue IF is then converted to the digital domain, with a 10-bit ADC,
clocked at 20.48MHz and the resulting Digital output is centered on 15.69MHz. This Digital signal is applied to the
ZL10310 via the ADC_IN[9:0] input pins, in the form of a 10-bit parallel signal.
The ZL10310 converts the digitized IF from a Terrestrial TV Tuner into an MPEG-2 Transport Stream, which can be
optionally de-scrambled (if CA scrambling is used by the broadcaster), and de-multiplexed into separate Packetised
Elementary Streams (PES), which are routed to the MPEG Audio and Video decoders, and SI data to the PowerPC
405TM subsystem.
Decoded Video can then be mixed and optionally scaled with On-Screen Display (OSD) Graphics generated by the
DTV application software. The resultant combination of video and graphics are then routed to the PAL/NTSC Digital
ENCoders (DENCs) for display on the TV via the on-chip 10-bit video DACs.
Decoded Audio is output directly from the audio decoder sub-system to the I2S and S/PDIF (Sony/Philips Digital
InterFace) outputs.
Zarlink Semiconductor Inc.
5
5 Page 
Data Sheet
ZL10310/ZL10311
6.0 ZL10310/ZL10311 388-pin Package Pin Descriptions
This section explains the ZL10310 and ZL10311 device pin functions. The following tables are segmented by signal
functions. Many of the pins listed below have multiple functions, and in these cases there is information on how the
multiplexed function connects to the pin.
Many references are made to register settings throughout the Pin Descriptions. The details of the ZL10310 and
ZL10311 registers can be found in the Hardware Design Manual for the ZL103xx family of Integrated Digital
Television Processors (Publication DM5797), available to customers on request, subject to NDA.
6.1 Pin Types
I An Input Type with no designator indicates that the signal must be produced by a device using 3.3V
outputs, and ESD protection is provided. There is no internal pull up, so unused inputs should be
tied high or low.
IO Pin Type indicates that the pin can be programmed with control bits to be used as an input or an
output.
B Pin Type indicates that the pin function can alternate between an input and output depending on the
use at that instant i.e. it is Bi-directional. Out characteristics are the same as an Out pin.
OD is an open drain Output.
O is a standard 3.3 V, 65 ohm, output, unless otherwise specified. DC drive is 8.2mA/5.4mA @ VH/VL
respectively. Maximum slew rate is 75mA/ns, unless otherwise specified.
5V is a 5V tolerant Input or Output. An Input Type with a 5V designator indicates that the input tolerates
5V signals. There is no internal pull up.
6.2 Front End Interfaces
Pin Name
ADCCLK
AGC[0]
AGC[1]
GPP[0]
GPP[1]
EXT_IN[0]
Pin
No.
Function
Pin
Type
Description
R02 ADCCLK
O Sampling Clock Output to External Tuner IF
Analog to Digital Converter. Clock = 20.48MHz.
L02 Tuner AGC control O 5V Master AGC Control Output to External TV Tuner
M03 Tuner AGC control O 5V Secondary AGC Control Output to External TV
offset
Tuner. Used to provide a differential AGC feed to
external TV Tuner, if required.
L01 Tuner_SCL
O 5V External TV Tuner Control Bus - Clock Output
N04 Tuner_SDA
K01 ED1_MDO[7]
(MSB)
B 5V External TV Tuner Control Bus - Data
Input/Output.
I External Demodulator 1 Digital Input -
Data Bit 7 (MSB)
DV2_IN_DATA[7]
(MSB)
I Reserved
RW_TDO
O Debug Interface - JTAG TDO (Data Out)
Notes
1
1
1, 6
1, 6
5, 7
7
3
Zarlink Semiconductor Inc.
11
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| PDF Descargar | [ Datasheet ZL10311.PDF ] | |
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