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PDF Z89390 Data sheet ( Hoja de datos )
| Número de pieza | Z89390 | |
| Descripción | 16-BIT DIGITAL SIGNAL PROCESSOR | |
| Fabricantes | Zilog. | |
| Logotipo |  |
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ZILOG
PRELIMINARY
Z89390
CPS DC-9030-01
PRELIMINARY
CUSTOMER PROCUREMENT SPECIFICATION
GENERAL DESCRIPTION
The Z89390 is a CMOS Digital Signal Processor (DSP).
Single-cycle instruction execution and a Harvard bus
structure promotes efficient algorithm execution. The
processor contains 512 word data RAM and 64K word of
external program address space is accessible. Six register
pointers provide circular buffering capabilities and dual
operand fetching. Three vectored interrupts are
complemented by a six level stack. The CODEC interface
enables high-speed transfer rates to accommodate digital
audio and voice data. A dedicated Counter/Timer provides
the necessary timing signals for the CODEC interface. An
additional 13-bit timer is available for general-purpose
use.
Z89390
16-BIT DIGITAL
SIGNAL PROCESSOR
Development tools for the IBM PC include a relocatable
assembler, a linker loader debugger.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.,
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Power
Ground
Circuit
VCC
GND
Device
VDD
V
SS
The Z89390 is optimized to accommodate intricate signal
processing algorithms. The 20-MIP operating performance
and efficient architecture provides real-time execution.
Compression, filtering, frequency detection, audio, voice
detection/synthesis and other available algorithms can all
be accommodated. The on-board peripherals provide
additional cost advantages.
DC 9030-00
1
1 page  
ZILOG P R E L I M I N A R Y
AC ELECTRICAL CHARACTERISTICS
(VDD = 5V 10%, TA = 0°C to +70°C unless otherwise specified)
Symbol
Parameter
Clock
TCY
Tr
Tf
CPW
Clock Cycle Time
Clock Rise Time
Clock Fall Time
Clock Pulse Width
I/O
DSSET
DSHOLD
EASET
EAHOLD
RDSET
RDHOLD
WRSET
WRHOLD
/DS Setup Time from CLOCK Fall
/DS Hold Time from CLOCK Rise
EA Setup Time to /DS Fall
EA Hold Time from /DS Rise
Data Read Setup Time to /DS Rise
Data Read Hold Time from /DS Rise
Data Write Setup Time to /DS Rise
Data Write Hold Time from /DS Rise
Interrupt
INTSET
Interrupt Setup Time to CLOCK Fall
INTWIDTH Interrupt Low Pulse Width
Codec Interface
SSET
FSSET
TXSET
RXSET
RXHOLD
SCLK Setup Time from Clock Rise
FSYNC Setup Time from SCLK Rise
TXD Setup Time from SCLK Rise
RXD Setup Time to SCLK Fall
RXD Hold Time from SCLK Fall
Min (ns)
50
23
0
4
12
4
14
6
5
7
1 TCY
7
0
Reset
RRISE
RSET
RWIDTH
Reset Rise Time
Reset Setup Time to CLOCK Rise
Interrupt Low Pulse Width
15
2 TCY
External Program Memory
PASET
PA Setup Time from CLOCK Rise
PDSET
PD Setup Time to CLOCK Rise
PDHOLD PD Hold Time from CLOCK Rise
5
10
10
Wait State
WSET
WHOLD
WAIT Setup Time to CLOCK Rise
WAIT Hold Time from CLOCK Rise
23
1
Halt
HSET
HHOLD
Halt Setup Time to CLOCK Rise
Halt Hold Time from CLOCK Rise
3
10
Max (ns)
2
2
15
15
18
15
6
7
1000
Z89390
CPS DC-9030-01
DC 9030-00
5
5 Page 
ZILOG
PRELIMINARY
Z89390
CPS DC-9030-01
© 1997 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
by Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of mer-
chantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.
Zilog’s products are not authorized for use as critical compo-
nents in life support devices or systems unless a specific written
agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
Telex 910-338-7621
FAX 408 370-8056
Internet: http://www.zilog.com
DC 9030-00
11
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet Z89390.PDF ] | |
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