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PDF Z86C33 Data sheet ( Hoja de datos )

Número de pieza Z86C33
Descripción CMOS Z8 CONSUMER CONTROLLER PROCESSOR
Fabricantes Zilog. 
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Z86C33/C43
CP95DZ80202
CUSTOMER PROCUREMENT SPECIFICATION
FEATURES
ROM
Part (KB)
Z86C33
4
Z86C43
4
* General-Purpose
RAM*
(Bytes)
237
236
Speed
(MHz)
12, 16
12, 16
s 40-Pin DIP, 44-Pin PLCC and QFP Packages (C43)
28-Pin DIP, 28-Pin SOIC (C33)
s 3.0- to 5.5-Volt Operating Range
s Low-Power Consumption
s –40°C to +105°C Operating Range
s Expanded Register File (ERF)
Z86C33/C43
CMOS Z8®
CONSUMER CONTROLLER PROCESSOR
s 32 Input/Output Lines (C43)
24 Input/Output Lines (C33)
s Vectored, Prioritized Interrupts with
Programmable Polarity
s Two Analog Comparators
s Two Programmable 8-Bit Counter/Timers,
Each with Two 6-Bit Programmable Prescaler
s Watch-Dog Timer (WDT)/Power-On Reset (POR)
s On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC, RC, or External Clock
s RAM and ROM Protect
GENERAL DESCRIPTION
The Z86C33/C43 Consumer Controller Processor (CCP)
is a member of Zilog's Z8® single-chip microcontroller
family with enhanced wake-up circuitry, programmable
Watch-Dog Timers (WDT), and low-noise/EMI options.
These enhancements result in a more efficient, cost-
effective design and provide the user with increased
design flexibility over the standard Z8 microcontroller
core. This low-power consumption CMOS microcontroller
offers fast execution, efficient use of memory, sophisti-
cated interrupts, input/output bit manipulation capabili-
ties, and easy hardware/software system expansion.
The Z86C33/C43 features an Expanded Register File
(ERF) to allow access to register-mapped peripheral and
I/O circuits. Four basic address spaces are available to
support this wide range of configurations: Program Memory,
Register File, Data Memory, and ERF. The Register File is
composed of 236 bytes of general-purpose registers, four
I/O port registers, and 15 control and status registers. The
ERF consists of three control registers
For applications demanding powerful I/O capabilities, the
Z86C33 provides 24 pins, and the Z86C43 provides 32
pins dedicated to input and output. These lines are
configurable under software control to provide timing,
status signals, parallel I/O with or without handshake, and
address/data bus for interfacing external memory.
To unburden the system from coping with real-time tasks
such as counting/timing and data communication, the
Z86C33/C43 offers two on-chip counter/timers with a large
number of user-selectable modes.
With ROM/ROMless selectivity, the Z86C43 provides both
external memory and pre-programmed ROM, which
enables this Z8 microcontroller to be used in high-volume
applications, or where code flexibility is required.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Power
Ground
Circuit
VCC
GND
Device
VDD
VSS
CP95DZ80202 9/95
1

1 page




Z86C33 pdf
PIN DESCRIPTION (Continued)
Z86C33/C43
CP95DZ80202
P21
P22
P23
P24
/DS
N/C
R//W
P25
P26
P27
P04
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11
12 Z86C43
35
34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
P30
P36
P37
P35
/RESET
R//RL
/AS
P34
P33
P32
P31
44-Pin PLCC Pin Assignments
44-Pin PLCC Pin Identification
Pin # Symbol Function
Direction
Pin # Symbol Function
Direction
1-2
3-4
5
6-10
11
GND
P12-13
P03
P20-24
/DS
Ground
Port 1, Pins 2,3
Port 0, Pin 3
Port 2, Pins 0,1,2,3,4
Data Strobe
In/Output
In/Output
In/Output
Output
28 XTAL1
29-31 P31-33
32 P34
33 /AS
34 R//RL
Crystal, Oscillator Clock Input
Port 3, Pins 1,2,3
Input
Port 3, Pin 4
Output
Address Strobe
Output
ROM/ROMless Control Input
12 N/C
13 R//W
14-16 P25-27
17-19 P04-06
20-21 P14-15
22
23,24
25-26
27
P07
VCC
P16-17
XTAL2
Not Connected
Read/Write
Port 2, Pins 5,6,7
Port 0, Pins 4,5,6
Port 1, Pins 4,5
Output
In/Output
In/Output
In/Output
Port 0, Pin 7
In/Output
Power Supply
Port 1, Pins 6,7
In/Output
Crystal, Oscillator Clock Output
35 /RESET
36 P35
37 P37
38 P36
39 P30
40-41 P00-01
42-43 P10-11
44 P02
Reset
Port 3, Pin 5
Port 3, Pin 7
Port 3, Pin 6
Port 3, Pin 0
Port 0, Pins 0,1
Port 1, Pins 0,1
Port 0, Pin 2
Input
Output
Output
Output
Input
In/Output
In/Output
In/Output
5

5 Page





Z86C33 arduino
Z86C33/C43
CP95DZ80202
AC CHARACTERISTICS
External I/O or Memory Read and Write Timing Table (C43 Only)
(SCLK/TCLK = XTAL/2)
No Symbol Parameter
TA=–0°C to 70°C
Note [3] 12 MHz 16 MHz
VCC Min Max Min Max
TA = –40°C to +105°C
12 MHz 16 MHz
Min Max Min Max
Units
Notes
1 TdA(AS) Address Valid to /AS Rise Delay
2 TdAS(A) /AS Rise to Address Float Delay
3.0 35
5.5 35
3.0 45
5.5 45
25
25
35
35
35 25 ns [2]
35 25
45 35 ns [2]
45 35 ns
3 TdAS(DR) /AS Rise to Read Data Req’d Valid
4 TwAS /AS Low Width
3.0
250 180
250
180 ns [1,2]
5.5
250 180
250
180 ns
3.0 55
40
55 40
ns [2]
5.5 55
40
55 40
ns
5 TdAS(DS) Address Float to /DS Fall
6 TwDSR /DS (Read) Low Width
3.0 0
5.5 0
3.0 200
5.5 200
0
0
135
135
00
00
200 135
200 135
ns
ns
ns [1,2]
ns
7 TwDSW /DS (Write) Low Width
8 TdDSR(DR) /DS Fall to Read Data Req’d Valid
3.0 110
80
110 80
5.5 110
80
110 80
3.0
150 75
150
75
5.5
150 75
150
75
ns [1,2]
ns
ns [1,2]
ns
9 ThDR(DS) Read Data to /DS Rise Hold Time
10 TdDS(A) /DS Rise to Address Active Delay
3.00 0
5.5 0
3.0 45
5.5 55
0
0
50
50
00
00
45 50
55 50
ns [2]
ns
ns [2]
ns
11 TdDS(AS) /DS Rise to /AS Fall Delay
12 TdR/W(AS) R//W Valid to /AS Rise Delay
3.0 30
5.5 45
3.0 45
5.5 45
35
35
25
25
30 35
45 55
45 25
45 25
ns [2]
ns
ns [2]
ns
13 TdDS(R/W) /DS Rise to R//W Not Valid
3.0
5.5
14 TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay 3.0
5.5
45
45
55
55
35
35
25
25
45 35
45 35
55 25
55 25
ns [2]
ns
ns [2]
ns
15 TdDS(DW) /DS Rise to Write Data Not Valid Delay 3.0 45
35
45 35
ns [2]
5.5 45
35
45 35
ns
16 TdA(DR) Address Valid to Read Data Req’d Valid 3.0
310 230
310
230 ns [1,2]
5.5
310 230
310
230 ns
17 TdAS(DS) /AS Rise to /DS Fall Delay
18 TdDM(AS) /DM Valid to /AS Fall Delay
19 TdDS(DM) /DS Rise to DM Valid Delay
20 ThDS(AS) /DS Valid to Address Valid Hold Time
3.0 65
5.5 65
3.0 35
5.5 35
45
45
45
45
45
45
30
30
35
35
35
35
65 45
65 45
35 30
35 30
45 35
45 35
45 35
45 35
ns [2]
ns
ns [2]
ns
ns
ns
ns
ns
Notes:
[1] When using extended memory timing add 2 TpC.
[2] Timing numbers given are for minimum TpC.
[3] The VCC voltage specification of 3.0V guarantees 3.3V ± 0.3V, and the
VDD voltage specification of 5.5V guarantees 5.0V ± 0.5V.
Standard Test Load
All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
11

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