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PDF Z86C21 Data sheet ( Hoja de datos )
| Número de pieza | Z86C21 | |
| Descripción | 8K ROM Z8 CMOS MICROCONTROLLER | |
| Fabricantes | Zilog. | |
| Logotipo |  |
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PRODUCT S PECIFICA TION
Z86C21 MCU
WITH 8K ROM
FEATURES
s 8-Bit CMOS MCU with 8 Kbytes of ROM
s 256 Byte Register File
- 236 Bytes of General-Purpose RAM
- 16 Bytes Control/Status Registers
- 4 Bytes for Ports
s 40-Pin DIP, 44-Pin PLCC or 44-Pin QFP Package
s 4.5V to 5.5V Operating Range
s Low Power Consumption: 220 mW (max) @ 16 MHz
s Fast instruction pointer: 1.0 µs @ 12 MHz
s Two Standby Modes: STOP and HALT
s 32 Input/Output Lines
Z86C21
8K ROM Z8® CMOS
MICROCONTROLLER
s Full-Duplex UART
s All Digital Inputs are TTL Levels
s Auto Latches
s RAM and ROM Protect
s Two Programmable 8-Bit Counter/Timers each with
6-Bit Programmable Prescaler.
s Six Vectored, Priority Interrupts from Eight Different
Sources
s Clock Speeds: 12 and 16 MHz
s On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC, or External Clock Drive.
GENERAL DESCRIPTION
The Z86C21 microcontroller is a member of the Z8 single-
chip microcontroller family with 8 Kbytes of ROM and
236 bytes of RAM. The device is packaged in a 40-pin DIP,
44-pin PLCC, or a 44-pin QFP with a ROMless pin option
available on the 44-pin versions only. With the ROM/
ROMless feature selectively, the Z86C21 offers both exter-
nal memory and preprogrammed ROM, making it well-
suited for high-volume applications or where code flexibil-
ity is required.
Zilog’s CMOS microcontroller offers fast execution, effi-
cient use of memory, sophisticated interrupts, input/output
bit manipulation capabilities, and easy hardware/software
system expansion along with low cost and low power
consumption.
The Z86C21 architecture is characterized by Zilog’s 8-bit
microcontroller core. The device offers a flexible I/O
scheme, an efficient register and address space structure,
multiplexed capabilities between address/data, I/O, and a
number of ancillary features that are useful in many indus-
trial and advanced scientific applications.
For applications demanding powerful I/O capabilities, the
Z86C21 provides 32 pins dedicated to input and output.
These lines are grouped into four ports. Each port consists
of eight lines, and is configurable under software control to
provide timing, status signals, serial or parallel
I/O with or without handshake, and an address/data bus
for interfacing external memory. There are three basic
address spaces available to support this configuration:
Program Memory, Data Memory, and 236 general-pur-
pose registers.
1
1 page  
Z86C21 MCU
WITH 8K ROM
/RESET
R//W
/DS
/AS
P35
GND
P32
P00
P01
P02
R//RL
33 32 31 30 29 28 27 26 25 24 23
34
35
36
37
38
39
Z86C21
QFP
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
1 2 3 4 5 6 7 8 9 10 11
GND
P24
P23
P22
P21
P20
P33
P34
P17
P16
P15
Figure 4. 44-Pin QFP Pin Assignments
Pin # Symbol
1-5
6
7-14
15
P03-P07
GND
P10-P17
P34
16
17-21
22
23-25
P33
P20-P24
GND
P25-P27
26 P31
27 P36
28 GND
29 V
CC
30 XTAL2
Table 3. 44-Pin QFP Pin Identification
Function
Direction Pin # Symbol Function
Direction
Port 0, Pins 3,4,5,6,7
Ground
Port 1, Pins 0 through 7
Port 3, Pin 4
In/Output
Input
In/Output
Output
31
32
33
34
XTAL1
P37
P30
/RESET
Crystal, Oscillator Clock
Port 3, Pin 7
Port 3, Pin 0
Reset
Input
Output
Input
Input
Port 3, Pin 3
Port 2, Pins 0,1,2,3,4
Ground
Port 2, Pins 5,6,7
Input
In/Output
Input
In/Output
35
36
37
38
R//W
/DS
/AS
P35
Read/Write
Data Strobe
Address Strobe
Port 3, Pin 5
Output
Output
Output
Output
Port 3, Pin 1
Port 3, Pin 6
Ground
Power Supply
Crystal, Oscillator Clock
Input
Output
Input
Input
Output
39
40
41-43
44
GND
P32
P00-P02
R//RL
Ground
Port 3, Pin 2
Port 0, Pins 0,1,2
ROM/ROMless control
Input
Input
In/Output
Input
5
5 Page 
Table 4. Port 3 Pin Assignments
Pin
I/O
CTC1
Int.
P0 HS
P1 HS
P30 IN
P31 IN
P32 IN
P33 IN
IRQ3
TIN IRQ2
IRQ0
D/R
IRQ1
D/R
P34 OUT
P35 OUT
P36 OUT
P37 OUT
T0
T1
T
OUT
IRQ4
IRQ5
R/D
R/D
Notes:
HS = Handshake Signals; D = Data Available; R = Ready
Z86C21 MCU
WITH 8K ROM
P2 HS
D/R
UART
Serial In
Ext
DM
R/D
Serial Out
Auto Latch. The Auto Latch puts valid CMOS levels on all
CMOS inputs that are not externally driven. This reduces
excessive supply current flow in the input buffer when it is
not been driven by any source.
Low EMI Option. The Z86C21 is available in a Low EMI
option. This option is mask-programmable, to be selected
by the customer at the time when the ROM code is
submitted. Use of this feature results in:
s The pre-drivers slew rate reduced to 10 ns typical.
s Low EMI output drivers have resistance of 200 Ohms
typical.
s Oscillator divide-by-two circuitry is eliminated.
s Internal SCLK/TCLK operation is limited to a maximum
of 4 MHz (250 ns cycle time)
Transmitted Data (No Parity)
SP SP D7 D6 D5 D4 D3 D2 D1 D0 ST
Start Bit
Eight Data Bits
Two Stop Bits
Received Data (No Parity)
SP D7 D6 D5 D4 D3 D2 D1 D0 ST
Start Bit
Eight Data Bits
One Stop Bit
Transmitted Data (With Parity)
SP SP P D6 D5 D4 D3 D2 D1 D0 ST
Start Bit
Seven Data Bits
Odd Parity
Two Stop Bits
Received Data (With Parity)
SP P D6 D5 D4 D3 D2 D1 D0 ST
Start Bit
Seven Data Bits
Parity Error Flag
One Stop Bit
Figure 9. Serial Data Formats
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet Z86C21.PDF ] | |
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