PDF XR17D158 Data sheet ( Hoja de datos )

Número de pieza	XR17D158
Descripción	UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
Fabricantes	Exar Corporation
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No Preview Available ! xr XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART NOVEMBER 2004 GENERAL DESCRIPTION FEATURES REV. 1.2.1 The XR17D1581 (D158) is an octal PCI Bus Universal Asynchronous Receiver and Transmitter (UART) with support for PCI Bus universal VIO buffers in the same package and pin-out as the XR17C158, XR17C154 and XR17D154. The device is designed to meet the 32-bit PCI Bus and high bandwidth requirement in communication systems. A global interrupt source register provides a complete interrupt status indication for all 8 channels to speed up interrupt parsing. Each UART has its own 16C550 compatible set of configuration registers, transmit and receive FIFOs of 64 bytes, fully programmable transmit and receive FIFO level trigger levels, transmit and receive FIFO level counters, automatic RTS/CTS or DTR/DSR hardware flow control with programmable hysteresis levels, automatic software (Xon/Xoff) flow control, IrDA (Infrared Data Association) encoder/decoder, 8 multi-purpose inputs/outputs and a 16-bit general purpose timer/ counter. NOTE: 1 Covered by U.S. Patents #5,649,122 and #5,949,787 APPLICATIONS • Universal Form Factor PCI Bus Add-in Card • Remote Access Servers • Network Management • Factory Automation and Process Control • Point-of-Sale Systems • Multi-port RS-232/RS-422/RS-485 Cards • High Performance Octal PCI UART • Universal PCI Bus Buffers - Auto-sense 3.3V or 5V Operation • 32-bit PCI Bus 2.3 Target Signalling Compliance • A Global Interrupt Source Register for all 8 UARTs • Data Transfer in Byte, Word and Double-word • Data Read/Write Burst Operation • Each UART is independently controlled with: ■ 16C550 Compatible 5G Register Set ■ 64-byte Transmit and Receive FIFOs ■ Transmit and Receive FIFO Level Counters ■ Programmable TX and RX FIFO Trigger Level ■ Automatic RTS/CTS or DTR/DSR Flow Control ■ Automatic Xon/Xoff Software Flow Control ■ RS485 HDX Control Output with Selectable Turn-around Delay ■ Infrared (IrDA 1.0) Data Encoder/Decoder ■ Programmable Data Rate with Prescaler ■ Up to 6.25 Mbps Serial Data Rate • Eight Multi-Purpose Inputs/outputs • A General Purpose 16-bit Timer/counter • Sleep Mode with Automatic Wake-up • EEPROM Interface for PCI Configuration • Same Package and Pin-out as the XR17C158, XR17C154 and XR17D154 FIGURE 1. BLOCK DIAGRAM 3.3V or 5V VIO CLK RST# AD[31:0] C/BE[3:0]# FRAME# IRDY# TRDY# DEVSEL# STOP# INTA# IDSEL PERR# SERR# PAR EECK EEDI EEDO EECS PCI Local Bus Interface Device Configuration Registers Configuration Space Registers EEPROM Interface 16-bit Timer/Counter UART Channel 0 UART Regs BRG 64 Byte TX FIFO TX & RX IR ENDEC 64 Byte RX FIFO UART Channel 1 UART Channel 2 UART Channel 3 UART Channel 4 UART Channel 5 UART Channel 6 UART Channel 7 Multi-pur.pose Inputs/Outputs Crystal Osc/Buffer 5V VCC (Core Logic) GND TX0, RX0, DTR0#, DSR0#, RTS0#, CTS0#, CD0#, RI0# TX7, RX7, DTR7#, DSR7#, RTS7#, CTS7#, CD7#, RI7# MPIO0- MPIO7 XTAL1 XTAL2 TMRCK Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com 1 page xr REV. 1.2.1 PIN DESCRIPTIONS NAME RTS4# CTS4# DTR4# DSR4# CD4# PIN # 86 82 87 83 84 RI4# 85 TX5 80 RX5 71 RTS5# CTS5# DTR5# DSR5# CD5# RI5# TX6 RX6 78 72 79 75 76 77 62 55 RTS6# CTS6# DTR6# DSR6# CD6# RI6# TX7 RX7 60 56 61 57 58 59 54 47 RTS7# CTS7# DTR7# DSR7# 52 48 53 49 XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART TYPE DESCRIPTION O UART channel 4 Request to Send or general purpose output (active low). I UART channel 4 Clear to Send or general purpose input (active low). O UART channel 4 Data Terminal Ready or general purpose output (active low). I UART channel 4 Data Set Ready or general purpose input (active low). I UART channel 4 Carrier Detect or general purpose input (active low). I UART channel 4 Ring Indicator or general purpose input (active low). O UART channel 5 Transmit Data or infrared transmit data. Normal TXD output idles HIGH while infrared TXD output idles LOW. I UART channel 5 Receive Data or infrared receive data. Normal RXD input idles HIGH. The infrared pulses typically idle LOW but can be inverted inter- nally prior the decoder by FCTR[4]. O UART channel 5 Request to Send or general purpose output (active low). I UART channel 5 Clear to Send or general purpose input (active low). O UART channel 5 Data Terminal Ready or general purpose output (active low). I UART channel 5 Data Set Ready or general purpose input (active low). I UART channel 5 Carrier Detect or general purpose input (active low). I UART channel 5 Ring Indicator or general purpose input (active low). O UART channel 6 Transmit Data or infrared transmit data. Normal TXD output idles HIGH while infrared TXD output idles LOW. I UART channel 6 Receive Data or infrared receive data. Normal RXD input idles HIGH. The infrared pulses typically idle LOW but can be inverted inter- nally prior the decoder by FCTR[4]. O UART channel 6 Request to Send or general purpose output (active low). I UART channel 6 Clear to Send or general purpose input (active low). O UART channel 6 Data Terminal Ready or general purpose output (active low). I UART channel 6 Data Set Ready or general purpose input (active low). I UART channel 6 Carrier Detect or general purpose input (active low). I UART channel 6 Ring Indicator or general purpose input (active low). O UART channel 7 Transmit Data or infrared transmit data. Normal TXD output idles HIGH while infrared TXD output idles LOW. I UART channel 7 Receive Data or infrared receive data. Normal RXD input idles HIGH. The infrared pulses typically idle LOW but can be inverted inter- nally prior the decoder by FCTR[4]. O UART channel 7 Request to Send or general purpose output (active low). I UART channel 7 Clear to Send or general purpose input (active low). O UART channel 7 Data Terminal Ready or general purpose output (active low). I UART channel 7 Data Set Ready or general purpose input (active low). 5 5 Page xr REV. 1.2.1 XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART 2.0 XR17D158 REGISTERS The XR17D158 UART has three different sets of registers as shown in Figure 5. The PCI local bus configuration space registers are for plug-and-play auto-configuration when connecting the device to a the PCI bus. This auto-configuration feature makes installation very easy into a PCI system and it is part of the PCI local bus specification. The second register set is the device configuration registers that are accessible directly from the PCI bus for programming general operating conditions of the device and monitoring the status of various functions. These registers are mapped into 4K of the PCI bus memory address space. These functions include all 8 channel UART’s interrupt control and status, 16-bit general purpose timer control and status, multipurpose inputs/outputs control and status, sleep mode, soft-reset, and device identification and revision. And lastly, each UART channel has its own set of internal UART configuration registers for its own operation control and status reporting. All 8 sets of channel registers are embedded inside the device configuration registers space, which provides faster access. The following paragraphs describe all 3 sets of registers in detail. FIGURE 5. THE XR17D158 REGISTER SETS D evic e C onfig ur ation and U AR T [7:0] C onfig uration R eg isters are mapped on to the Base Address R eg ister (BAR ) in a 4K- byte of memor y addr es s space PC I Local Bus Inter fac e PC I Local Bus C onfig uration Space R eg isters for Plug - and-Play Auto C onfig uration Vendor and Sub- vendor ID and Product M odel N umber in Exter nal EEPR O M C hannel 0 IN T , M PIO , T IM ER ,R EG C hannel 0 C hannel 1 C hannel 2 C hannel 3 C hannel 4 C hannel 5 C hannel 6 C hannel 7 0 x0 0 0 0 0 x0 0 8 0 0 x0 2 0 0 0 x0 4 0 0 0 x0 6 0 0 0 x0 8 0 0 0x0A 00 0x0C 00 0 x0 E 0 0 0x0F F F D evic e C onfig ur ation R eg is ter s 8 channel Interrupts, M ultipurpose I/O s, 16-bit T imer/C ounter, Sleep, R eset, D VID , D R EV U AR T [7:0] C onfig uration R eg isters 16550 C ompatible and EXAR Enhanced R eg isters PCIREG S-1 2.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS The PCI local bus configuration space registers are responsible for setting up the device’s operating environment in the PCI local bus. The pre-defined operating parameters of the device is read by the PCI bus plug-and-play auto-configuration manager in the operating system. After the PCI bus has collected all data from every device/card on the bus, it defines and downloads the memory mapping information to each device/ card about their individual operation memory address location and conditions. The operating memory mapped address location is downloaded into the Base Address Register (BAR) register, 0x10. The plug-and-play auto configuration feature is only available when an external 93C46 EEPROM is used. The EEPROM contains the device vendor and sub-vendor data required by the auto-configuration setup. 11 11 Page

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