PDF XR16L788 Data sheet ( Hoja de datos )

Número de pieza	XR16L788
Descripción	HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART
Fabricantes	Exar Corporation
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No Preview Available ! XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART JULY 2008 REV. 1.2.3 GENERAL DESCRIPTION The XR16L7881 (788), is a 2.97V to 5.5V with 5V tolerant inputs octal Universal Asynchronous Receiver and Transmitter (UART). The highly integrated device is designed for high bandwidth requirement in communication systems. The global interrupt source register provides a complete interrupt status indication for all 8 channels to speed up interrupt parsing. Each UART has its own 16C550 compatible set of configuration registers, TX and RX FIFOs of 64 bytes, fully programmable transmit and receive FIFO trigger levels, TX and RX FIFO level counters, automatic RTS/CTS or DTR/DSR hardware flow control with programmable hysteresis, autoamtic software (Xon/Xoff) flow control, RS-485 half-duplex direction control with programmable turn-around delay, Intel or Motorola bus interface and sleep mode with a wake-up indicator. NOTE: Covered by US patents #5,649,122 and #5,949,787 APPLICATIONS • Remote Access Servers • Ethernet Network to Serial Ports • Network Management • Factory Automation and Process Control • Point-of-Sale Systems • Multi-port RS-232/RS-422/RS-485 Cards FEATURES • 2.97V to 5.5V with 5V Tolerant Inputs Operation • Single Interrupt Output for all 8 UARTs • Global Interrupt Source for all 8 UARTs • 5G “Flat” UART Registers for Configurations • Simultaneous UART Channels Initialization • Auto RS485 Half-duplex Control with Program- mable Turn-around Delay • A General Purpose 16-bit Timer/Counter • Sleep Mode with Wake-up Indication • Highly Integrated Device for Space Saving • First eight registers are 16C550 compatible • 64-byte Transmit and Receive FIFOs • Transmit and Receive FIFO Level Counters • Programmable TX and RX FIFO Trigger Levels • Automatic RTS/CTS or DTR/DSR Flow Control • Selectable Hardware Flow Control Hysteresis • Automatic Xon/Xoff Software Flow Control with Status Indicator • Infrared (IrDA 1.0) Data Encoder/Decoder • Programmable Data Rate with Prescaler • Up to 6.25 Mbps Serial Data Rate at 5V • 100-pin QFP Package (14x20x3 mm) FIGURE 1. BLOCK DIAGRAM RST# A7:A0 D7:D0 IOR# IOW# CS# INT# 16/68# Data Bus Interface Device Configuration Registers 16-bit Timer/Counter UART Channel 0 UART Regs BRG 64 Byte TX FIFO TX & RX IR ENDEC 64 Byte RX FIFO UART Channel 1 UART Channel 2 UART Channel 3 UART Channel 4 UART Channel 5 UART Channel 6 UART Channel 7 Crystal Osc/Buffer TX0, RX0, DTR0#, DSR0#, RTS0#, CTS0#, CD0#, RI0# TX7, RX7, DTR7#, DSR7#, RTS7#, CTS7#, CD7#, RI7# XTAL1 XTAL2 TMRCK Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com 1 page REV. 1.2.3 NAME TX4 RX4 RTS4# CTS4# DTR4# DSR4# CD4# RI4# TX5 RX5 RTS5# CTS5# DTR5# DSR5# CD5# RI5# TX6 RX6 RTS6# CTS6# DTR6# DSR6# CD6# RI6# TX7 PIN # 64 57 62 58 63 59 60 61 56 49 54 50 55 51 52 53 46 39 44 40 45 41 42 43 38 XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART TYPE DESCRIPTION O UART channel 4 Transmit Data or infrared transmit data. I UART channel 4 Receive Data or infrared receive data. Normal RXD input idles HIGH. The infrared pulses can be inverted internally prior the decoder by FCTR[4]. O UART channel 4 Request to Send or general purpose output (active low). See description of RTS0# pin. I UART channel 4 Clear to Send or general purpose input (active low). See description of CTS0# pin. O UART channel 4 Data Terminal Ready or general purpose output (active low). See description of DTR0# pin. I UART channel 4 Data Set Ready or general purpose input (active low). See description of DSR0# pin. I UART channel 4 Carrier Detect or general purpose input (active low). I UART channel 4 Ring Indicator or general purpose input (active low). O UART channel 5 Transmit Data or infrared transmit data. I UART channel 5 Receive Data or infrared receive data. Normal RXD input idles HIGH. The infrared pulses can be inverted internally prior the decoder by FCTR[4]. O UART channel 5 Request to Send or general purpose output (active low). See description of RTS0# pin. I UART channel 5 Clear to Send or general purpose input (active low). See description of CTS0# pin. O UART channel 5 Data Terminal Ready or general purpose output (active low). See description of DTR0# pin. I UART channel 5 Data Set Ready or general purpose input (active low). See description of DSR0# pin. I UART channel 5 Carrier Detect or general purpose input (active low). I UART channel 5 Ring Indicator or general purpose input (active low). O UART channel 6 Transmit Data or infrared transmit data. I UART channel 6 Receive Data or infrared receive data. Normal RXD input idles HIGH. The infrared pulses can be inverted internally prior the decoder by FCTR[4]. O UART channel 6 Request to Send or general purpose output (active low). See description of RTS0# pin. I UART channel 6 Clear to Send or general purpose input (active low). See description of CTS0# pin. O UART channel 6 Data Terminal Ready or general purpose output (active low). See description of DTR0# pin. I UART channel 6 Data Set Ready or general purpose input (active low). See description of DSR0# pin. I UART channel 6 Carrier Detect or general purpose input (active low). I UART channel 6 Ring Indicator or general purpose input (active low). O UART channel 7 Transmit Data or infrared transmit data. 5 5 Page REV. 1.2.3 XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART FIGURE 6. TRANSMITTER OPERATION IN NON-FIFO MODE Data Byte Transmit Holding Register (THR) THR Interrupt (ISR bit-1) Enabled by IER bit-1 16X or 8X Clock Transmit Shift Register (TSR) ML SS BB TXNOFIFO1 2.7.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty. FIGURE 7. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE Transmit Data Byte Auto CTS Flow Control (CTS# pin) Flow Control Characters (Xoff1/2 and Xon1/2 Reg. Auto Software Flow Control T ransm it FIFO THR Interrupt (ISR bit-1) falls below the programmed Trigger Level and then when becomes empty. FIFO is Enabled by FCR bit-0=1 16X or 8X Clock Transmit Data Shift Register (TSR) T XF IF O 1 2.8 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the 16X for timing. It verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16X. After 8 clocks the start bit period should be at the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7- 4.6 character times. The RHR interrupt is enabled by IER bit-0. 11 11 Page

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