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PDF M48Z19 Data sheet ( Hoja de datos )
| Número de pieza | M48Z19 | |
| Descripción | CMOS 8K x 8 ZEROPOWER SRAM | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M48Z09
M48Z19
CMOS 8K x 8 ZEROPOWER SRAM
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
UNLIMITED WRITE CYCLES
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
POWER-FAIL INTERRUPT
CHOICE of TWO WRITE PROTECT
VOLTAGES:
– M48Z09: 4.5V ≤ VPFD ≤ 4.75V
– M48Z19: 4.2V ≤ VPFD ≤ 4.5V
SELF CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
11 YEARS of DATA RETENTION in the
ABSENCE of POWER
PIN and FUNCTION COMPATIBLE with the
MK48Z09, 19 and JEDEC STANDARD 8K x 8
SRAMs
28
1
PCDIP28 (PC)
Battery CAPHAT
Figure 1. Logic Diagram
DESCRIPTION
The M48Z09,19 ZEROPOWER® RAM is an 8K x 8
non-volatile static RAM which is pin and function
compatible with the MK48Z09,19.
A special 28 pin 600mil DIP CAPHAT™ package
houses the M48Z09,19 silicon with a long life lith-
ium button cell to form a highly integrated battery
backed-up memory solution.
Table 1. Signal Names
A0-A12
Address Inputs
DQ0-DQ7 Data Inputs / Outputs
INT Power Fail Interrupt
E1 Chip Enable 1
E2 Chip Enable 2
G Output Enable
W Write Enable
VCC Supply Voltage
VSS Ground
VCC
13
A0-A12
8
DQ0-DQ7
W
M48Z09
E1 M48Z19 INT
E2
G
VSS
AI01184
November 1994
1/13
1 page  
M48Z09, M48Z19
Table 7. Power Down/Up Mode AC Characteristics (TA = 0 to 70°C)
Symbol
Parameter
Min Max Unit
tPD
tF (1)
tFB (2)
E1 or W at VIH or E2 at VIL before Power Down
VPFD (max) to VPFD (min) VCC Fall Time
VPFD (min) to VSO VCC Fall Time
0
300
10
µs
µs
µs
tR VPFD(min) to VPFD (max) VCC Rise Time
0 µs
tRB VSO to VPFD (min) VCC Rise Time
1 µs
tREC E1 or W at VIH or E2 at VIL after Power Up
1 ms
tPFX INT Low to Auto Deselect
10 40 µs
tPFH(3)
VPFD (max) to INT High
120 µs
Notes: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
VCC passes VPFD (min).
2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
3. INT may go high anytime after VCC exceeds VPFD (min) and is guaranteed to go high tPFH after VCC exceeds VPFD (max).
Figure 5. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tPD
tF
INT
tFB
tPFX
INPUTS
RECOGNIZED
OUTPUTS
VALID
(PER CONTROL INPUT)
tDR
tRB
DON'T CARE
HIGH-Z
tR
tPFH
NOTE
tREC
RECOGNIZED
VALID
(PER CONTROL INPUT)
AI00566
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E1 high or E2 low as VCC rises past VPFD(min).
Some systems may performs inadvertent write cycles after VCC rises above VPFD(min) but before normal system operations begins. Even
though a power on reset is being applied to the processor a reset condition may not occur until after the system clock is running.
5/13
5 Page 
ORDERING INFORMATION SCHEME
Example:
M48Z09
-100 PC 1
M48Z09, M48Z19
Supply Voltage and Write
Protect Voltage
09 VCC = 4.75V to 5.5V
VPFD = 4.5V to 4.75V
19 VCC = 4.5V to 5.5V
VPFD = 4.2V to 4.5V
Speed
-100 100ns
Package
PC PCDIP28
Temp. Range
1 0 to 70 °C
For a list of available options (Supply Voltage, Speed, Package, etc...) refer to the current Memory
Shortform catalogue.
For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office
nearest to you.
11/13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet M48Z19.PDF ] | |
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