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PDF SAA7705H Data sheet ( Hoja de datos )
| Número de pieza | SAA7705H | |
| Descripción | Car radio Digital Signal Processor DSP | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
SAA7705H
Car radio Digital Signal Processor
(DSP)
Preliminary specification
File under Integrated Circuits, IC01
1999 Aug 16
1 page  
Philips Semiconductors
Car radio Digital Signal Processor (DSP)
Preliminary specification
SAA7705H
SYMBOL
PARAMETER
CONDITIONS
MIN.
S/NAM
THDTAPE
S/NTAPE
Vi(con)(max)(rms)
signal-to-noise ratio AM
inputs
total harmonic distortion
TAPE inputs
signal-to-noise ratio
TAPE inputs
maximum conversion
input level at analog
inputs (RMS value)
input signal at 1 kHz;
0 dB reference = 0.55 V (RMS);
bandwidth = 5 kHz
input signal 0.55 V (RMS) at
1 kHz; bandwidth = 20 kHz;
input signal at 1 kHz;
0 dB reference = 0.55 V (RMS);
bandwidth = 20 kHz
THD < 1%
83
−
−
81
0.6
Analog outputs; Tamb = 25 °C; VDDA2 = 3.3 V; unless otherwise specified
(THD + N)/S
total harmonic
distortion-plus-noise to
signal ratio
output signal 0.72 V (RMS) at
f = 1 kHz; RL > 5 kΩ (AC);
A-weighted
−
DR
dynamic range
output signal −60 dB at 1 kHz; 92
0 dB reference = 0.77 V (RMS);
A-weighted
DS digital silence output signal at
−
20 Hz to 17 kHz;
0 dB reference = 0.77 V (RMS);
A-weighted
Oscillator (fosc = 11.2896 MHz)
fxtal
fclk(DSP)
crystal frequency
clock frequency
DSP core
−
−
Note
1. FMRDS and FMMPX input sensitivity setting ‘000’ (see Table 17).
TYP. MAX. UNIT
88 −
dB
−80 −76 dB
0.01 0.016 %
83 −
dB
0.66 −
V
−75 −65 dBA
102 −
dBA
−108 −102 dBA
11.2896 −
27.1656 −
MHz
MHz
5 ORDERING INFORMATION
TYPE
NUMBER
SAA7705H
NAME
QFP80
PACKAGE
DESCRIPTION
plastic quad flat package; 80 leads (lead length 1.95 mm);
body 14 × 20 × 2.8 mm
VERSION
SOT318-2
1999 Aug 16
5
5 Page 
Philips Semiconductors
Car radio Digital Signal Processor (DSP)
Preliminary specification
SAA7705H
8 FUNCTIONAL DESCRIPTION
The SAA7705H consists of a DSP core and periphery.
The DSP core is described in Sections 8.6, 8.7 and 8.11.
The periphery handles the following tasks:
• FM and level information processing (see Section 8.1)
• Analog source selection and analog-to-digital
conversion of the analog audio sources (see
Section 8.2)
• Digital-to-analog conversion of the DSP output QDAC
(see Section 8.3)
• Clock circuit and oscillator (see Section 8.4)
• Equalizer accelerator circuit (see Section 8.5)
• I2C-bus interface (see Section 8.8 and Chapter 12)
• RDS decoder (see Section 8.10).
8.1 FM and level information processing
8.1.1 SIGNAL PATH FOR LEVEL INFORMATION
For FM weak signal processing and for AM and FM
purposes (absolute level and multipath), an FM level and
an AM level input is implemented (pins FML and AML).
In the case of radio reception clocking of the filters and the
level-ADC is based on a 38 kHz sample frequency.
The DC input signal is converted by a bitstream first-order
Sigma-Delta ADC followed by a decimation filter.
The input signal has to be obtained from the radio part.
Two different configurations for AM and FM reception are
possible:
• A circuit with two separate level signals: one for FM level
and one for AM level
• A combined circuit with AM and FM level information on
the FM level input.
The level input is selected with bit LEVAM-FM of the SEL
register (see Table 12 and Chapter 12).
8.1.2
SIGNAL PATH FROM FMMPX INPUT TO IAC AND
STEREO DECODER
The SAA7705H has four analog audio source channels.
One of the analog inputs is the FM multiplex signal.
Selection of this signal can be achieved by the SEL
register bits AUX-FM and CD-TAPE (see Table 12).
The multiplexed FM signal is converted to the digital
domain in SCAD1, a bitstream third-order SCAD. The first
decimation with a factor of 16 takes place in down sample
filter ADF1. This decimation filter can be switched by
means of the SEL register bit WIDE-NARROW
(see Table 12) in the wide or narrow band position. In case
of FM reception, it must be in the narrow position.
The FMMPX path is followed by the sample-and-hold
switch of the IAC (see Section 8.1.5) and the 19 kHz pilot
signal regeneration circuit. A second decimation filter
reduces the output of the IAC to a lower sample rate.
One of the two filter outputs contains the multiplexed
signal with a frequency range of 0 to 60 kHz.
The outputs of this signal path to the DSP (which are all
running on a sample frequency of 38 kHz) are:
• Pilot presence indication: Pilot-I. This one bit signal is
LOW for a pilot frequency deviation <4 kHz and HIGH
for a pilot frequency deviation >4 kHz and locked on a
pilot tone.
• FM reception stereo signal. This is the 18-bit output of
the stereo decoder after the matrix decoding in
Information System Network (ISN) I2S-bus format.
This signal is fed via a multiplexer to a general I2S-bus
interface block that communicates with the DSP core.
• A noise level indication. This signal is derived from the
first MPX decimation filter via a wide band noise filter.
Detection is done with an envelope detector. This noise
level is filtered in the DSP core and is used to optimize
the FM weak signal processing.
8.1.3 INPUT SENSITIVITY FOR FM AND RDS SIGNALS
The FM and RDS input sensitivity is designed for tuner
front ends which deliver an output voltage varying from
65 to 225 mV (RMS) at a sweep of 22.5 kHz for a 1 kHz
tone. The intermediate standard input sensitivities can be
reached in steps of 1.6 dB, to be programmed with the
AD register bits VOLFM and VOLRDS (see Tables 9
and 17). The volume control of the FMMPX and the
FMRDS input can be controlled separately. VOLFM and
VOLRDS = 000 is the most sensitive position, VOLFM and
VOLRDS = 111 the least sensitive position. Due to the
analog circuit control of the volume gain, the input
impedance of pin FMMPX or pin FMRDS changes with the
volume setting.
8.1.4 AD INPUT SELECTION SWITCH
Pin SELFR makes it possible to change to another
transmitter frequency with the same radio program to
assess the quality of that signal. In case of a stronger
transmitter signal the decision can be made by the
software to switch to the new transmitter. The FMMPX
input is normally used to process the FM signal.
This FMMPX input is connected via a relative large
capacitor to the MPX tuner output. Switching the tuner to
another transmitter frequency means another DC voltage
level on the MPX output of the tuner and a charging of the
1999 Aug 16
11
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