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PDF SAA7366T Data sheet ( Hoja de datos )
| Número de pieza | SAA7366T | |
| Descripción | Bitstream conversion ADC for digital audio systems | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
SAA7366
Bitstream conversion ADC for
digital audio systems
Preliminary specification
File under Integrated Circuits, IC01
May 1994
Philips Semiconductors
1 page  
Philips Semiconductors
Bitstream conversion ADC for
digital audio systems
Preliminary specification
SAA7366
SFOR 1
STD 2
OVLD 3
CKIN 4
VDDD 5
VSSD 6
SDO 7
SWS 8
SCK 9
TEST1 10
HPEN 11
TEST2 12
24 SLAVE
23 VDDA
22 VREFL
21 BIL
20 BOL
SAA7366
19 VDACP
18 VDACN
17 BOR
16 BIR
15 VREFR
14 I REF
13 VSSA
MGA912
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
General
The SAA7366 is a bitstream conversion CMOS ADC for
digital audio systems. The conversion is achieved using a
third order Sigma-Delta modulator (SDM), operating at
128 times the output sample frequency (fs). The high
oversampling ratio greatly simplifies the design of the
analog input anti-alias filter. In most cases the internal
buffer operational amplifier, configured as a low-pass filter
will suffice. The 1-bit code from the Sigma-Delta modulator
is filtered and down-sampled (decimated) to 1fs in two
stages of filtering. An optional high-pass filter is provided
to remove DC, if required. The device has been designed
with ease of use, low board area and low application costs
in mind.
Clock frequency
The external clock, input on pin CKIN, operates at
256 times fs, which can range from 18 kHz to 53 kHz.
Input buffer
Two input buffers are provided, one for each channel, for
signal amplitude matching, signal buffering and anti-alias
filter purposes. These are configured for inverting use.
Access is provided by pins BIL, BIR (inverting inputs) and
BOL, BOR (outputs) for left and right channels
respectively. By the choice of feedback component values,
the application signal amplitude can be matched to the
requirements of the ADC. Typically the operational
amplifiers are configured as low-pass filters with a gain
of 1 and a pole at approximately 5fs.
Remark: The complete ADC is non-inverting. Hence a
positive DC input (referenced to Vref) will yield a positive
digital output.
Input level
The overall system gain is proportional VDDA, or more
accurately {V(VDACP) − V(VDACN)}. For convenience the
ADC input signal amplitude is defined as that amplitude
seen on BOL or BOR, the operational amplifier outputs
(i.e. the input to the Sigma-Delta modulator). Also, the
0 dB input level is defined as that which provides a −1 dB
(actually −1.08 dB) digital output, relative to full-scale
swing. This offset provides headroom to accommodate
small random DC offsets without causing the digital output
to clip.
Hence:
VI (0 dB) = V------(---V----D---A----C---P----)----5–-----V-----(---V----D----A---C----N---)-- = V (RMS)
The user of the IC should ensure, that when all sources of
signal amplitude variation are taken into account, the
maximum input signal should conform to the 0 dB level. If
not, clipping may occur. In the event that the maximum
signal level cannot be pre-determined, e.g. a live
microphone input, the average signal level should be set
at −10 to −20 dB down. The exact value will depend on the
application and the balance between head room and
operating signal-to-noise ratio.
Behaviour during overload
As defined earlier the maximum input level for normal
operation is 0 dB. If the input level exceeds this value
clipping may occur. Infringements are limited to the
maximum permitted positive or negative values, 217 − 1 or
−217 respectively. If the high-pass filter has been enabled
the clipped output samples may have non-maximum
values due to the removal of the DC content. Input signals
in the range of 0 to 1 dB may or may not be clipped
depending on the values of DC dither and small random
offsets in the analog circuitry.
When using the recommended application circuitry,
clipping will initially be observed on negative peaks due to
the use of negative DC dither.
The maximum level of overload that can be safely
tolerated is application circuit dependent. In the case of the
May 1994
5
5 Page 
FORMAT 2
SWS
FORMAT 1
SCK
SDO
LEFT DATA
1 STEREO WORD
RIGHT DATA
LEFT DATA
18 CLOCKS
14 CLOCKS
RIGHT DATA
18 CLOCKS
14 CLOCKS
MSB
LSB
MSB
LSB
MSB
MGA914
Fig.3 Serial interface master mode format.
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet SAA7366T.PDF ] | |
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