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PDF SAA7128H Data sheet ( Hoja de datos )
| Número de pieza | SAA7128H | |
| Descripción | Digital video encoder | |
| Fabricantes | NXP Semiconductors | |
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SAA7128H; SAA7129H
Digital video encoder
Rev. 03 — 9 December 2004
Product data sheet
1. General description
The SAA7128H; SAA7129H encodes digital CR-Y-CB video data to an NTSC, PAL or
SECAM CVBS or S-video signal. Simultaneously, RGB or bypassed but interpolated
CR-Y-CB signals are available via three additional DACs. The circuit at a 54 MHz
multiplexed digital D1 input port accepts two ITU-R BT.656 compatible CR-Y-CB data
streams with 720 active pixels per line in 4 : 2 : 2 multiplexed formats, for example MPEG
decoded data with overlay and MPEG decoded data without overlay, where one data
stream is latched at the rising clock edge and the other at the falling clock edge.
It includes a sync/clock generator and on-chip DACs.
2. Features
s Monolithic CMOS 3.3 V device, 5 V I2C-bus optional
s Digital PAL/NTSC/SECAM encoder
s System pixel frequency 13.5 MHz
s 54 MHz double-speed multiplexed D1 interface capable of splitting data into two
separate channels (encoded and baseband)
s Three Digital-to-Analog Converters (DACs) for CVBS (CSYNC), VBS (CVBS) and C
(CVBS) two times oversampled with 10-bit resolution (signals in brackets optional)
s Three DACs for RED (CR), GREEN (Y) and BLUE (CB) two times oversampled with
9-bit resolution (signals in brackets optional)
s An advanced composite sync is available on the CVBS output for RGB display
centering
s Real-time control of subcarrier
s Cross-color reduction filter
s Closed captioning encoding and World Standard Teletext (WST) and North-American
Broadcast Text System (NABTS) teletext encoding including sequencer and filter
s Copy Generation Management System (CGMS) encoding (CGMS described by
standard CPR-1204 of EIAJ); 20 bits in lines 20/283 (NTSC) can be loaded via I2C-bus
s Fast I2C-bus control port (400 kHz)
s Line 23 Wide Screen Signalling (WSS) encoding
s Video Programming System (VPS) data encoding in line 16 (50/625 lines counting)
s Encoder can be master or slave
s Programmable horizontal and vertical input synchronization phase
s Programmable horizontal sync output phase
s Internal Color Bar Generator (CBG)
1 page  
Philips Semiconductors
SAA7128H; SAA7129H
Digital video encoder
Table 3:
Symbol
MP7
MP6
MP5
MP4
MP3
MP2
MP1
MP0
VDDD2
VSSD2
RTCI
Pinning…continued
Pin Type
9I
10 I
11 I
12 I
13 I
14 I
15 I
16 I
17 supply
18 supply
19 I
VDD(I2C)
SA
20
21
VSSA1
RED
C
VDDA1
GREEN
VBS
VDDA2
BLUE
CVBS
VDDA3
VSSA2
VSSA3
XTALO
XTALI
22
23
24
25
26
27
28
29
30
31
32
33
34
35
VDDA4
XCLK
36
37
VSSD3
VDDD3
RESET_N
38
39
40
supply
I
supply
O
O
supply
O
O
supply
O
O
supply
supply
supply
O
I
supply
O
supply
supply
I
SCL
SDA
TTXRQ
TTX
41
42
43
44
I/(O)
I/O
O
I
Description
double-speed 54 MHz MPEG port; it is an input for ITU-R BT.656 style multiplexed
CR-Y-CB data; data is sampled on the rising and falling clock edge; data sampled on the
rising edge is then sent to the encoding part of the device; data sampled on the falling
edge is sent to the RGB part of the device (or vice versa, depending on programming)
digital supply voltage 2
digital ground 2
real-time control input; if the LLC1 clock is provided by an SAA7113 or SAA7118, RTCI
should be connected to the RTCO pin of the respective decoder to improve the signal
quality
sense input for I2C-bus voltage; connect to I2C-bus supply
select I2C-bus address; LOW selects slave address 88h, HIGH selects slave address
8Ch
analog ground 1 for RED (CR), C (CVBS) and GREEN (Y) outputs
analog output of RED (CR) signal
analog output of chrominance (CVBS) signal
analog supply voltage 1 for RED (CR) and C (CVBS) outputs
analog output of GREEN (Y) signal
analog output of VBS (CVBS) signal
analog supply voltage 2 for VBS (CVBS) and GREEN (Y) outputs
analog output of BLUE (CB) signal
analog output of CVBS (CSYNC) signal
analog supply voltage 3 for BLUE (CB) and CVBS (CSYNC) outputs
analog ground 2 for VBS (CVBS), BLUE (CB) and CVBS (CSYNC) outputs
analog ground 3 for the DAC reference ladder and the oscillator
crystal oscillator output
crystal oscillator input; if the oscillator is not used, this pin should be connected to
ground
analog supply voltage 4 for the DAC reference ladder and the oscillator
clock output of the crystal oscillator
digital ground 3
digital supply voltage 3
Reset input, active LOW. After reset is applied, all digital I/Os are in input mode; PAL
black burst on CVBS, VBS and C; RGB outputs set to lowest voltage. The I2C-bus
receiver waits for the START condition.
serial clock input (I2C-bus) with inactive output path
serial data input/output (I2C-bus)
teletext request output, indicating when text bits are requested
teletext bit stream input
9397 750 14325
Product data sheet
Rev. 03 — 9 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5 of 55
5 Page 
Philips Semiconductors
SAA7128H; SAA7129H
Digital video encoder
TTXRQ provides a fully programmable request signal to the teletext source, indicating the
insertion period of bitstream at lines which are selectable independently for both fields.
The internal insertion window for text is set to 360 (PAL-WST), 296 (NTSC-WST) or 288
(NABTS) teletext bits including clock run-in bits. The protocol and timing are illustrated in
Figure 23.
7.3.3 Video Programming System (VPS) encoding
Five bytes of VPS information can be loaded via the I2C-bus and will be encoded in the
appropriate format into line 16.
7.3.4 Closed caption encoder
Using this circuit, data in accordance with the specification of closed caption or extended
data service, delivered by the control interface, can be encoded (line 21). Two dedicated
pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code,
are possible.
The actual line number where data is to be encoded in, can be modified in a certain range.
The data clock frequency is in accordance with the definition for NTSC-M standard
32 times horizontal line frequency.
Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the
DACs corresponds to approximately 50 IRE.
It is also possible to encode closed caption data for 50 Hz field frequencies at 32 times
horizontal line frequency.
7.3.5 Anti-taping (SAA7128H only)
For more information contact your nearest Philips Semiconductors sales office.
7.4 RGB processor
This block contains a dematrix in order to produce red, green and blue signals to be fed to
a SCART plug.
Before Y, CB and CR signals are de-matrixed, individual gain adjustment for Y and color
difference signals and 2 times oversampling for luminance and 4 times oversampling for
color difference signals is performed. The transfer curves of luminance and color
difference components of RGB are illustrated in Figure 12 and Figure 13 respectively.
7.5 SECAM processor
SECAM specific pre-processing is achieved by a pre-emphasis of color difference signals
(for gain and phase see Figure 14 and Figure 15 respectively).
A baseband frequency modulator with a reference frequency shifted from 4.286 MHz to
DC carries out SECAM modulation in accordance with appropriate standard or optional
wide clipping limits.
After HF pre-emphasis, line-by-line sequential carriers with black reference of 4.25 MHz
(Db) and 4.40625 MHz (Dr) are generated on a DC reference carrier (anti-Cloche filter;
see Figure 16 and Figure 17) using specified values for FSC programming bytes.
9397 750 14325
Product data sheet
Rev. 03 — 9 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11 of 55
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SAA7128H.PDF ] | |
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