PDF SAA7105E Data sheet ( Hoja de datos )

Número de pieza	SAA7105E
Descripción	Digital video encoder
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET SAA7104E; SAA7105E Digital video encoder Product speciﬁcation 2004 Mar 04 1 page This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... VDDA1 VDDA2 VDDA3 VDDA4 VSSA1 VSSA2 VDDD1 VDDD2 VDDD3 VDDD4 VSSD1 VSSD2 VSSD3 VSSD4 A10, B9, B6 D6 B6 B8 A8 F4 D4 D4 D4 C5, D5, C5, D5, C5, D5, C5, D5, C9, D9 E4 E4 E4 E4 PD11 to PD0 C1, C2, B1, B2, A2, B4, B3, A3, F3, H1, H2, H3 INPUT FORMATTER F2 PIXCLKI DECIMATOR 4 : 4 : 4 to 4:2:2 FIFO + UPSAMPLING HORIZONTAL SCALER LUT + CURSOR VERTICAL SCALER RGB TO Y-CB-CR MATRIX VERTICAL FILTER A4 A7, B7 A9 B5 D1 D3 E1 TRST DUMP RSET TDI TDO TMS TCK PIXCLKO G4 FIFO BORDER GENERATOR VIDEO ENCODER TRIPLE DAC SAA7104E SAA7105E HD OUTPUT PIXEL CLOCK SYNTHESIZER CRYSTAL OSCILLATOR TIMING GENERATOR I2C-BUS CONTROL A5 A6 C3 G1 F1 G3 E3 C4 G2 E2 D2 XTALI XTALO FSVGC CBO TTXRQ_XCLKO2 SDA SCL RESET 27 MHz VSVGC HSVGC TTX_SRES C6 BLUE_CB_CVBS C7 GREEN_VBS_CVBS C8 RED_CR_C_CVBS D7 VSM D8 HSM_CSYNC F12 TVD mhc572 Fig.1 Block diagram. 5 Page Philips Semiconductors Digital video encoder Product speciﬁcation SAA7104E; SAA7105E 7.3 RGB LUT The three 256 byte RAMs of this block can be addressed by three 8-bit wide signals, thus it can be used to build any transformation, e.g. a gamma correction for RGB signals. In the event that the indexed colour data is applied, the RAMs are addressed in parallel. The LUTs can either be loaded by an I2C-bus write access or can be part of the pixel data input through the PD port. In the latter case, 256 × 3 bytes for the R, G and B LUT are expected at the beginning of the input video line, two lines before the line that has been defined as first active line, until the middle of the line immediately preceding the first active line. The first 3 bytes represent the first RGB LUT data, and so on. 7.4 Cursor insertion A 32 × 32 dots cursor can be overlaid as an option; the bit map of the cursor can be uploaded by an I2C-bus write access to specific registers or in the pixel data input through the PD port. In the latter case, the 256 bytes defining the cursor bit map (2 bits per pixel) are expected immediately following the last RGB LUT data in the line preceding the first active line. The cursor bit map is set up as follows: each pixel occupies 2 bits. The meaning of these bits depends on the CMODE I2C-bus register as described in Table 5. Transparent means that the input pixels are passed through, the ‘cursor colours’ can be programmed in separate registers. The bit map is stored with 4 pixels per byte, aligned to the least significant bit. So the first pixel is in bits 0 and 1, the next pixel in bits 3 and 4 and so on. The first index is the column, followed by the row; index 0,0 is the upper left corner. Table 3 Layout of a byte in the cursor bit map D7 D6 pixel n + 3 D1 D0 D5 D4 pixel n + 2 D1 D0 D3 D2 pixel n + 1 D1 D0 D1 D0 pixel n D1 D0 For each direction, there are 2 registers controlling the position of the cursor, one controls the position of the ‘hot spot’, the other register controls the insertion position. The hot spot is the ‘tip’ of the pointer arrow. It can have any position in the bit map. The actual position registers describe the co-ordinates of the hot spot. Again 0,0 is the upper left corner. While it is not possible to move the hot spot beyond the left respectively upper screen border this is perfectly legal for the right respectively lower border. It should be noted that the cursor position is described relative to the input resolution. Table 4 Cursor bit map BYTE 0 1 2 ... 6 7 ... 254 255 D7 D6 D5 D4 D3 D2 D1 D0 row 0 row 0 row 0 row 0 column 3 column 2 column 1 column 0 row 0 row 0 row 0 row 0 column 7 column 6 column 5 column 4 row 0 column 11 row 0 column 10 row 0 row 0 column 9 column 8 ... ... ... ... row 0 column 27 row 0 column 26 row 0 column 25 row 0 column 24 row 0 column 31 row 0 column 30 row 0 column 29 row 0 column 28 ... ... ... ... row 31 column 27 row 31 column 26 row 31 column 25 row 31 column 24 row 31 column 31 row 31 column 30 row 31 column 29 row 31 column 28 Table 5 Cursor modes CURSOR PATTERN CURSOR MODE CMODE = 0 CMODE = 1 00 second cursor colour second cursor colour 01 ﬁrst cursor colour ﬁrst cursor colour 10 transparent transparent 11 inverted input auxiliary cursor colour 2004 Mar 04 11 11 Page

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