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PDF SAA6712E Data sheet ( Hoja de datos )
| Número de pieza | SAA6712E | |
| Descripción | XGA RGB to TFT graphics engine | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
SAA6712E
XGA RGB to TFT graphics engine
Preliminary specification
File under Integrated Circuits, IC02
1999 Aug 25
1 page  
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VCLK
VVS
VHS
CLAMP
GAINC
VPA7 to VPA0
VPB7 to VPB0
VPC7 to VPC0
VPD7 to VPD0
VPE7 to VPE0
VPF7 to VPF0
MCLKI
CLK
SDA
INT
SCL SAD RST
OVA2 to OVA0 OVVS
TDO
TMS TCLK
OVB2
to
TDI TRST OVACT OVB0
OVHS
OVCLK
MODE/SYNC
DETECTION
input frame size and
sync information
AUTO
ADJUSTMENT
CONTROLLER
RGB
raw data
frequency, phase and
colour information
LINE MEMORY
I2C-BUS
INTERFACE
GLOBAL CONTROL
UNIT
JTAG
CONTROLLER
RGB
data DOWN-
SCALER
RGB
INPUT
INTERFACE
SDRAM
MEMORY INTERFACE
UP-
SCALER
COLOUR
CORRECTION
PANNING
UNIT
ON
SCREEN
DISPLAY
TEMPORAL
DITHERING
memory
clock
÷2
PLL
DIVIDER
panel
clock
DQ63 to DQ0 BA
RAS WE
DQM A10 to A0 CAS MCLKO
SAA6712E
OSD
OVERLAY
PORT
OUTPUT
INTERFACE
PAR7 to PAR0
PAG7 to PAG0
PAB7 to PAB0
PBR7 to PBR0
PBG7 to PBG0
PBB7 to PBB0
PVS
PHS
PDE
PCLK
MHB456
Fig.1 Block diagram.
5 Page 
Philips Semiconductors
XGA RGB to TFT graphics engine
Preliminary specification
SAA6712E
SYMBOL
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
TCLK
TRST
TDI
TMS
TDO
Pin PORT
H18 memory interface
G18 memory interface
F19 memory interface
A12 memory interface
B12 memory interface
A13 memory interface
B13 memory interface
A14 memory interface
B14 memory interface
A15 memory interface
B15 memory interface
A16 memory interface
C15 memory interface
C14 memory interface
D14 memory interface
C13 memory interface
C12 memory interface
D12 memory interface
C11 memory interface
B7 memory interface
A7 memory interface
B8 memory interface
A8 memory interface
B9 memory interface
A9 memory interface
B10 memory interface
A10 memory interface
B11 memory interface
A11 memory interface
D10 memory interface
C10 memory interface
D9 memory interface
C9 memory interface
C8 memory interface
D7 memory interface
U19 JTAG test controller
W17
U18
V19
W19
I/O(1)
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input
input
input
input
output
DESCRIPTION
memory data bus
JTAG test controller clock; note 2
JTAG test controller reset (active LOW); note 2
JTAG test data input; note 2
JTAG test mode select; note 2
JTAG test data output
1999 Aug 25
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SAA6712E.PDF ] | |
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