SCAN928028 Datasheet PDF - National Semiconductor
| Part Number | SCAN928028 | |
| Description | 8 Channel 10:1 Serializer with IEEE 1149.1 and At-Speed BIST | |
| Manufacturers | National Semiconductor | |
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September 2003
SCAN928028
8 Channel 10:1 Serializer with IEEE 1149.1 and At-Speed
BIST
General Description
The SCAN928028 integrates eight serializer devices into a
single chip. The SCAN928028 can simultaneously serialize
up to eight 10-bit data streams. The 10-bit parallel inputs are
LVTTL signal levels. The serialized outputs are LVDS signals
with extra drive current for point-to-point and lightly loaded
multidrop applications. Each serializer block in the
SCAN928028 operates independently by using strobes from
a single shared PLL.
The SCAN928028 uses a single +3.3V power supply with a
typical power dissipation of 740mW (3.3V / PRBS / 66 MHz).
Each serializer channel has a unique power down control to
further conserve power consumption.
For high-speed LVDS serial data transmission, line quality is
essential, thus the SCAN928028 includes an @SPEED
TEST function. Each Serializer channel has the ability to
internally generate a PRBS data pattern. This pattern is
received by specific deserializers (SCAN921224) which
have the complement PRBS verification circuit. The deseri-
alizer checks the data pattern for bit errors and reports any
errors on the test verification pins on the deserializer.
For additional information - please see the Applications
Information section in this datasheet.
Features
n IEEE 1149.1 (JTAG) Compliant and At-Speed BIST test
mode.
n All 8 channels synchronous to one parallel clock rate,
from 25 to 66 MHz
n Duplicates function of multiple DS92LV1021 and ’1023
10-bit Serializer devices
n Serializes from one to eight 10-bit parallel inputs into
data streams with embedded clock
n Eight 5 mA modified Bus LVDS outputs that are capable
to drive double terminations
n @Speed Test - PRBS generation to check LVDS
transmission path to SCAN921224, SCAN921226,
SCAN921260, or SCAN926260
n On chip filtering for PLL
n 740mW typ power dissipation (loaded, PRBS, 66MHz,
3.3V)
n High impedance inputs and outputs on power off
n Single power supply at +3.3V (+/-10%)
n 196-pin LBGA package
n Industrial temperature range operation: -40 to +85˚C
Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2003 National Semiconductor Corporation DS200521
20052115
www.national.com
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Serializer Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3)
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
tRJIT
Random Jitter
RL = 100Ω,
CL=10pF to GND
(Note 5)
(Note 6)
25MHz
66MHz
39
18
tDJIT
Deterministic Jitter,
Figure 10
RL = 100Ω,
CL=10pF to GND
(Note 5)
(Note 7)
25MHz
66MHz
−225
−150
20
−55
Max
45
21
257
68
Units
ps
(rms)
ps
(rms)
ps
(p-p)
ps
(p-p)
SCAN Circuitry Timing Requirements
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
fMAX
tS
tH
tS
tH
tW
tW
tREC
Maximum TCK Clock
Frequency
TDI to TCK, H or L
TDI to TCK, H or L
TMS to TCK, H or L
TMS to TCK, H or L
TCK Pulse Width, H or L
TRST Pulse Width, L
Recovery Time, TRST to
TCK
RL = 500Ω,
CL = 35 pF
25
2.0
1.0
2.0
1.0
10.0
2.5
2.5
Max
Units
MHz
ns
ns
ns
ns
ns
ns
ns
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for VCC = 3.3V and TA = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, and ∆VOD
which are differential voltages.
Note 4: BIST_SEL have a weak internal pull-up. In a noisy operating environment, it is recommended that an external pull up be used to ensure that BIST_SEL is
in the high state.
Note 5: tLLHT, tLHLT, tDJIT and tRJIT specifications are Guaranteed by Design using statistical analysis.
Note 6: tRJIT specification is the rms jitter measurement of the serializer output when the device is transmitting SYNC pattern.
Note 7: tDJIT specification is measured with the serializer output transmitting checkerboard patterns. It is a measurement of the center distribution of 0V (differential)
crossing in comparsion with the ideal bit position. See Figure 10
AC Timing Diagrams and Test Circuits
20052103
FIGURE 1. ’Worst Case Icc Test Pattern
5
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| Information | Total 18 Pages | |
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