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PDF SC16C652 Data sheet ( Hoja de datos )
| Número de pieza | SC16C652 | |
| Descripción | Dual UART | |
| Fabricantes | NXP Semiconductors | |
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SC16C652
Dual UART with 32 bytes of transmit and receive FIFOs
Rev. 04 — 20 June 2003
Product data
1. Description
The SC16C652 is a 2 channel Universal Asynchronous Receiver and Transmitter
(UART) used for serial data communications. Its principal function is to convert
parallel data into serial data and vice versa. The UART can handle serial data rates
up to 5 Mbits/s. The SC16C652 is pin compatible with the SC16C2550. It will
power-up to be functionally equivalent to the 16C2450. The SC16C652 provides
enhanced UART functions with 32-byte FIFOs, modem control interface, DMA mode
data transfer. The DMA mode data transfer is controlled by the FIFO trigger levels
and the TXRDY and RXRDY signals. On-board status registers provide the user with
error indications and operational status. System interrupts and modem control
features may be tailored by software to meet specific user requirements. An internal
loop-back capability allows on-board diagnostics. Independent programmable baud
rate generators are provided to select transmit and receive baud rates.
The SC16C652 operates at 5 V, 3.3 V and 2.5 V and the Industrial temperature
range, and is available in a plastic LQFP48 package.
2. Features
s 2 channel UART
s 5 V, 3.3 V and 2.5 V operation
s Industrial temperature range
s Pin and functionally compatible to 16C2450 and software compatible with
SC16C650
s Up to 5 Mbits/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V
s 32-byte transmit FIFO to reduce the bandwidth requirement of the external CPU
s 32-byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU
s Independent transmit and receive UART control
s Four selectable Receive and Transmit FIFO interrupt trigger levels
s Automatic software/hardware flow control
s Programmable Xon/Xoff characters
s Software selectable Baud Rate Generator
s Sleep mode
s Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun
Break)
s Transmit, Receive, Line Status, and Data Set interrupts independently controlled
1 page  
Philips Semiconductors
SC16C652
Dual UART with 32 bytes of transmit and receive FIFOs
Table 2: Pin description…continued
Symbol
Pin Type Description
LQFP48
INTA, INTB 30, 29 O
Interrupt A, B (3-State). This function is associated with individual channel interrupts,
INTA, INTB. INTA, INTB are enabled when MCR bit 3 is set to a logic 1, interrupts are
enabled in the interrupt enable register (IER), and is active when an interrupt condition
exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit
buffer empty, or when a modem status flag is detected.
IOR 19 I Read strobe (Active-LOW strobe). A logic 0 transition on this pin will load the contents
of an internal register defined by address bits A0-A2 onto the SC16C652 data bus
(D0-D7) for access by external CPU.
IOW 15 I Write strobe (Active-LOW strobe). A logic 0 transition on this pin will transfer the
contents of the data bus (D0-D7) from the external CPU to an internal register that is
defined by address bits A0-A2.
OP2A,
OP2B
32, 9
O Output 2 (user-defined). This function is associated with individual channels, A through
B. The state at these pin(s) are defined by the user and through MCR register bit 3. INTA,
INTB are set to the active mode and OP2 to logic 0 when MCR[3] is set to a logic 1. INTA,
INTB are set to the 3-State mode and OP2 to a logic 1 when MCR[3] is set to a logic 0.
See bit 3, Modem Control Register (MCR[3]). Since these bits control both the INTA,
INTB operation and OP2 outputs, only one function should be used at one time, INT or
OP2.
RESET
36
I Reset (Active-HIGH). A logic 1 on this pin will reset the internal registers and all the
outputs. The UART transmitter output and the receiver input will be disabled during reset
time. (See Section 7.11 “SC16C652 external reset condition” for initialization details.)
RXRDYA,
RXRDYB
31, 18
O
Receive Ready A, B (Active-LOW). This function provides the RX FIFO/RHR status for
individual receive channels (A-B). RXRDYn is primarily intended for monitoring DMA
mode 1 transfers for the receive data FIFOs. A logic 0 indicates there is a receive data to
read/upload, i.e., receive ready status with one or more RX characters available in the
FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty or when the programmed
trigger level has not been reached. This signal can also be used for single mode transfers
(DMA mode 0).
TXRDYA,
TXRDYB
43, 6
O Transmit Ready A, B (Active-LOW). These outputs provide the TX FIFO/THR status for
individual transmit channels (A-B). TXRDYn is primarily intended for monitoring DMA
mode 1 transfers for the transmit data FIFOs. An individual channel’s TXRDYA, TXRDYB
buffer ready status is indicated by logic 0, i.e., at lease one location is empty and
available in the FIFO or THR. This pin goes to a logic 1 (DMA mode 1) when there are no
more empty locations in the FIFO or THR. This signal can also be used for single mode
transfers (DMA mode 0).
VCC
XTAL1
42
13
I Power supply input.
I Crystal or external clock input. Functions as a crystal input or as an external clock
input. A crystal can be connected between this pin and XTAL2 to form an internal
oscillator circuit. This configuration requires an external 1 MΩ resistor between the
XTAL1 and XTAL2 pins. Alternatively, an external clock can be connected to this pin to
provide custom data rates. (See Section 6.8 “Programmable baud rate generator”.)
See Figure 3.
XTAL2
14
O Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal oscillator
output or buffered clock output. Should be left open if an external clock is connected to
XTAL1. For extended frequency operation, this pin should be tied to VCC via a 2 kΩ
resistor.
CDA, CDB 40, 16 I
Carrier Detect (Active-LOW). These inputs are associated with individual UART
channels A through B. A logic 0 on this pin indicates that a carrier has been detected by
the modem for that channel.
9397 750 11634
Product data
Rev. 04 — 20 June 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
5 of 41
5 Page 
Philips Semiconductors
SC16C652
Dual UART with 32 bytes of transmit and receive FIFOs
6.8 Programmable baud rate generator
The SC16C652 supports high speed modem technologies that have increased input
data rates by employing data compression schemes. For example, a 33.6 kbit/s
modem that employs data compression may require a 115.2 kbit/s input data rate.
A 128.0 kbit/s ISDN modem that supports data compression may need an input
data rate of 460.8 kbit/s. The SC16C652 can support a standard data rate of
921.6 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generator is
capable of operating with a frequency of up to 80 MHz. To obtain maximum data rate,
it is necessary to use full rail swing on the clock input. The SC16C652 can be
configured for internal or external clock operation. For internal clock oscillator
operation, an industry standard microprocessor crystal is connected externally
between the XTAL1 and XTAL2 pins. Alternatively, an external clock can be
connected to the XTAL1 pin to clock the internal baud rate generator for standard or
custom rates (see Table 6).
The generator divides the input 16× clock by any divisor from 1 to 216 − 1. The
SC16C652 divides the basic external clock by 16. The basic 16× clock provides table
rates to support standard and custom applications using the same system design.
The rate table is configured via the DLL and DLM internal register functions.
Customized Baud Rates can be achieved by selecting the proper divisor values for
the MSB and LSB sections of baud rate generator.
Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB)
provides a user capability for selecting the desired final baud rate. The example in
Table 6 shows the selectable baud rate table available when using a 1.8432 MHz
external clock input.
X1
1.8432 MHz
C1
47 pF
C2
100 pF
Fig 3. Crystal oscillator connection.
1.5 kΩ
X1
1.8432 MHz
C1
22 pF
C2
47 pF
002aaa169
9397 750 11634
Product data
Rev. 04 — 20 June 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
11 of 41
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SC16C652.PDF ] | |
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