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PDF SC16C550IN40 Data sheet ( Hoja de datos )
| Número de pieza | SC16C550IN40 | |
| Descripción | Universal Asynchronous Receiver/Transmitter (UART) with 16-byte FIFO and infrared (IrDA) encoder/decoder | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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SC16C550
Universal Asynchronous Receiver/Transmitter (UART)
with 16-byte FIFO and infrared (IrDA) encoder/decoder
Rev. 05 — 19 June 2003
Product data
1. General description
The SC16C550 is a Universal Asynchronous Receiver and Transmitter (UART) used
for serial data communications. Its principal function is to convert parallel data into
serial data, and vice versa. The UART can handle serial data rates up to 3 Mbits/s.
The SC16C550 is pin compatible with the ST16C550, TL16C550 and PC16C550,
and it will power-up to be functionally equivalent to the 16C450. Programming of
control registers enables the added features of the SC16C550. Some of these added
features are the 16-byte receive and transmit FIFOs, automatic hardware or software
flow control and Infrared encoding/decoding. The selectable auto-flow control feature
significantly reduces software overload and increases system efficiency while in FIFO
mode by automatically controlling serial data flow using RTS output and CTS input
signals. The SC16C550 also provides DMA mode data transfers through FIFO trigger
levels and the TXRDY and RXRDY signals. On-board status registers provide the
user with error indications, operational status, and modem interface control. System
interrupts may be tailored to meet user requirements. An internal loop-back capability
allows on-board diagnostics.
The SC16C550 operates at 5 V, 3.3 V and 2.5 V, and the Industrial temperature
range, and is available in plastic DIP40, PLCC44 and LQFP48 packages.
2. Features
s 5 V, 3.3 V and 2.5 V operation
s Industrial temperature range
s After reset, all registers are identical to the typical 16C450 register set
s Capable of running with all existing generic 16C450 software
s Pin compatibility with the industry-standard ST16C450/550, TL16C450/550,
PC16C450/550
s Up to 3 Mbits/s transmit/receive operation at 5 V, 2 Mbits/s at 3.3 V, and
1 Mbit/s at 2.5 V
s 16 byte transmit FIFO
s 16 byte receive FIFO with error flags
s Programmable auto-RTS and auto-CTS
x In auto-CTS mode, CTS controls transmitter
x In auto-RTS mode, RxFIFO contents and threshold control RTS
s Automatic software/hardware flow control
s Programmable Xon/Xoff characters
s Software selectable Baud Rate Generator
s Four selectable Receive FIFO interrupt trigger levels
1 page  
Philips Semiconductors
SC16C550
UART with 16-byte FIFO and IrDA encoder/decoder
NC 1
D5 2
D6 3
D7 4
RCLK 5
NC 6
RX 7
TX 8
CS0 9
CS1 10
CS2 11
BAUDOUT 12
Fig 3. LQFP48.
SC16C550IB48
36 NC
35 MR
34 OUT1
33 DTR
32 RTS
31 OUT2
30 INT
29 RXRDY
28 A0
27 A1
26 A2
25 NC
002aaa093
9397 750 11619
Product data
Rev. 05 — 19 June 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
5 of 52
5 Page 
Philips Semiconductors
SC16C550
UART with 16-byte FIFO and IrDA encoder/decoder
Table 4: Flow control mechanism
Selected trigger level
(characters)
INT pin activation
11
44
88
14 14
Negate RTS or
send Xoff
4
8
12
14
Assert RTS or
send Xon
1
4
8
10
6.3 Autoflow control (see Figure 5)
Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS
input must be active before the transmitter FIFO can emit data. With auto-RTS, RTS
becomes active when the receiver needs more data and notifies the sending serial
device. When RTS is connected to CTS, data transmission does not occur unless the
receiver FIFO has space for the data; thus, overrun errors are eliminated using
UART 1 and UART 2 from a SC16C550 with the autoflow control enabled. If not,
overrun errors occur when the transmit data rate exceeds the receiver FIFO read
latency.
ACE1
ACE2
D7 – D0
RCV
FIFO
XMT
FIFO
SERIAL TO
PARALLEL
FLOW
CONTROL
PARALLEL
TO SERIAL
FLOW
CONTROL
RX
RTS
TX
CTS
TX
CTS
RX
RTS
PARALLEL
TO SERIAL
FLOW
CONTROL
SERIAL TO
PARALLEL
FLOW
CONTROL
Fig 5. Autoflow control (auto-RTS and auto-CTS) example.
XMT
FIFO
RCV
FIFO
D7 – D0
002aaa048
6.3.1 Auto-RTS (see Figure 5)
Auto-RTS data flow control originates in the receiver timing and control block (see
Figure 1 “Block diagram.”) and is linked to the programmed receiver FIFO trigger
level. When the receiver FIFO level reaches a trigger level of 1, 4, or 8 (see Figure 7),
RTS is de-asserted. With trigger levels of 1, 4, and 8, the sending UART may send an
additional byte after the trigger level is reached (assuming the sending UART has
another byte to send) because it may not recognize the de-assertion of RTS until
after it has begun sending the additional byte. RTS is automatically reasserted once
the RX FIFO is emptied by reading the receiver buffer register. When the trigger level
is 14 (see Figure 8), RTS is de-asserted after the first data bit of the 16th character is
present on the RX line. RTS is reasserted when the RX FIFO has at least one
available byte space.
9397 750 11619
Product data
Rev. 05 — 19 June 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
11 of 52
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