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PDF SC1164 Data sheet ( Hoja de datos )

Número de pieza SC1164
Descripción PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER/ DUAL LOW DROPOUT REGULATOR CONTROLLER
Fabricantes Semtech Corporation 
Logotipo Semtech Corporation Logotipo



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No Preview Available ! SC1164 Hoja de datos, Descripción, Manual

October 25, 1999
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1164/5
TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
DESCRIPTION
The SC1164/5 combines a synchronous voltage mode
controller with two low-dropout linear regulators
providing most of the circuitry necessary to implement
three DC/DC converters for powering advanced
microprocessors such as Pentium® II.
The SC1164/5 switching section features an integrated
5 bit D/A converter, pulse by pulse current limiting,
integrated power good signaling, and logic compatible
shutdown. The SC1164/5 switching section operates at
a fixed frequency of 200kHz, providing an optimum
compromise between size, efficiency and cost in the
intended application areas. The integrated D/A con-
verter provides programmability of output voltage from
2.0V to 3.5V in 100mV increments and 1.30V to 2.05V
in 50mV increments with no external components.
The SC1164/5 linear sections are low dropout regula-
tors. The SC1164 supplies 1.5V for GTL bus and 2.5V
for non-GTL I/O.
For the SC1165 both LDO’s are adjustable.
FEATURES
Synchronous design, enables no heatsink solution
95% efficiency (switching section)
5 bit DAC for output programmability
On chip power good function
Designed for Intel Pentium® ll requirements
1.5V, 2.5V or Adj. @ 1% for linear section
APPLICATIONS
Pentium® ll or Deschutes microprocessor supplies
Flexible motherboards
1.3V to 3.5V microprocessor supplies
Programmable triple power supplies
ORDERING INFORMATION
Part Number(1) Package
SC1164CSW SO-24
Linear
Voltage
Temp.
Range (TJ)
1.5V/2.5V 0° to 125°C
SC1165CSW SO-24
Adj. 0° to 125°C
Note:
(1) Add suffix ‘TR’ for tape and reel.
PIN CONFIGURATION
BLOCK DIAGRAM
Top View
AGND
GATE1
LDOS1
LDOS2
VCC
OVP
PWRGOOD
CS-
CS+
PGNDH
DH
PGNDL
1
2
3
4
5
6
7
8
9
10
11
12
24 GATE2
23 LDOV
22 VID0
21 VID1
20 VID2
19 VID3
18 VID4
17 VOSENSE
16 EN
15 BSTH
14 BSTL
13 DL
(24 Pin SOIC)
REF.
FET
CONTROLLER
2.5V/ADJ.
1.265V
REF.
LDOV
FET
CONTROLLER
1.5V/ADJ.
© 1999 SEMTECH CORP.
Pentium is a registered trademark of Intel Corporation
1
652 MITCHELL ROAD NEWBURY PARK CA 91320

1 page




SC1164 pdf
October 25, 1999
APPLICATION CIRCUIT
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1164/5
© 1999 SEMTECH CORP.
5
652 MITCHELL ROAD NEWBURY PARK CA 91320

5 Page





SC1164 arduino
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1164/5
October 25, 1999
FET type RDS(on) (m) PD (W) Package
BUK556H 22
IRL2203 7.0
2.48
0.79
TO220
D2PAK
Si4410 13.5
1.53 SO-8
BOTTOM FET - Bottom FET losses are almost entirely
due to conduction. The body diode is forced into conduc-
tion at the beginning and end of the bottom switch con-
duction period, so when the FET turns on and off, there
is very little voltage across it, resulting in low switching
losses. Conduction losses for the FET can be deter-
mined by:
INPUT CAPACITORS - since the RMS ripple current in
the input capacitors may be as high as 50% of the out-
put current, suitable capacitors must be chosen ac-
cordingly. Also, during fast load transients, there may
be restrictions on input di/dt. These restrictions require
useable energy storage within the converter circuitry,
either as extra output capacitance or, more usually,
additional input capacitors. Choosing low ESR input
capacitors will help maximize ripple rating for a given
size.
PCOND = IO2 R DS (on ) (1 − δ )
For the example above:
FET type
BUK556H
IRL2203
Si4410
RDS(on) (m) PD (W)
22 1.95
7.0 0.62
13.5 1.20
Package
TO220
D2PAK
SO-8
Each of the package types has a characteristic thermal
impedance, for the TO-220 package, thermal impedance
is mostly determined by the heatsink used. For the sur-
face mount packages on double sided FR4, 2 oz printed
circuit board material, thermal impedances of 40oC/W
for the D2PAK and 80oC/W for the SO-8 are readily
achievable. The corresponding temperature rise is de-
tailed below:
Temperature rise (oC)
FET type Top FET
BUK556H 49.6(1)
Bottom FET
39.0(1)
IRL2203 31.6
24.8
Si4410 122.4
96
(1) With 20oC/W Heatsink
It is apparent that single SO-8 Si4410 are not adequate for
this application, but by using parallel pairs in each posi-
tion, power dissipation will be approximately halved and
temperature rise reduced by a factor of 4.
© 1999 SEMTECH CORP.
11
652 MITCHELL ROAD NEWBURY PARK CA 91320

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