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PDF SM5950AM Data sheet ( Hoja de datos )
| Número de pieza | SM5950AM | |
| Descripción | Asynchronous Sample Rate Converter | |
| Fabricantes | Nippon Precision Circuits Inc | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SM5950AM (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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SM5950AM
Asynchronous Sample Rate Converter
OVERVIEW
The SM5950AM is a digital audio signal asynchronous sample rate converter LSI. It supports 16/20/24-bit
word-length input/output interface data. It also features a built-in digital deemphasis filter and direct mute
functions.
FEATURES
Functions
I L/R 2-channel (stereo) processing
I Input sample rate range: 20kHz to 100kHz
I Output sample rate range: 30kHz to 50kHz
I Operating sample rate conversion ratio (fso/fsi)*1
: 0.45 to 2.205 selectable
*1: fsi = input sample rate
fso = output sample rate
I Asynchronous input and output clock timing
I System clock input
• Input system clock: 1fsi (LRCI)
• Output system clock: 512fso (SCKO input)
I Deemphasis filter function
• IIR-type filter
• fsi = 44.1kHz, 48kHz, 32kHz compatible
I Direct mute function
I Through mode operation
• Direct connection from input to output
I Output data clocks (LRCO, BCKO)
• Slave mode: external inputs
• Master mode: derived from the output system
clock (SCKO)
I Computation round-off processing
• Normal round-off
I 5V tolerant input pins for direct connection to 5V
operation devices
I 3.3V single supply
I Package: 24-pin SSOP
PINOUT
(Top view)
LRCI 1
BCKI 2
DI 3
TMOD0 4
RSTN 5
VDD 6
IISI 7
IMOD0 8
IMOD1 9
DEEM 10
FS0 11
FS1 12
24 LRCO
23 BCKO
22 DOUT
21 SLAVE
20 SCKO
19 VSS
18 IISO
17 OMOD0
16 OMOD1
15 TMOD1
14 THROU
13 DMUTE
PACKAGE DIMENSIONS
(Unit: mm)
Weight: 0.23g
10.20 ± 0.30
10.05 ± 0.20
0.15
+
−
0.10
0.05
ORDERING INFORMATION
Device
SM5950AM
Package
24-pin SSOP
0.8 0.36 ± 0.10 0.12 M
0.10
0 to 10
Note: Dimensions without tolerance are reference values.
NIPPON PRECISION CIRCUITS INC.—1
1 page  
SM5950AM
SPECIFICATIONS
Absolute Maximum Ratings
VSS = 0V, VDD pin voltage = VDD
Parameter
Symbol
Supply voltage range
Input voltage range
Output voltage range
Storage temperature range
Power dissipation
VDD
VI
VO
Tstg
PD
Note: Ratings also apply at supply switch ON and OFF.
Rating
− 0.3 to 4.6
− 0.3 to 5.5
– 0.3 to VDD + 0.3
− 55 to 125
400
Recommended Operating Conditions
VSS = 0V, VDD pin voltage = VDD
Unit
V
V
V
°C
mW
Parameter
Supply voltage
Operating temperature
Symbol
VDD
Topr
min
3.0
– 40
Rating
typ
3.3
25
max
3.6
85
Unit
V
°C
DC Electrical Characteristics
VSS = 0V, VDD = 3.0 to 3.6V, Ta = −40 to 85°C
Parameter
Current consumption
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
Input leakage current
Pin
VDD
(*1) (*3)
(*2) (*3)
(*1) (*3)
Symbol
Condition
IDD (*A)
VIH
VIL
VOH IOH = −2.0mA
VOL IOL = 2.0mA
ILH VIN = VDD
ILL VIN = 0V
Rating
min typ max
– 22.0 30.0
2.0 – 5.5
0 – 0.7
2.4 – VDD
0 – 0.4
– 1.0 –
1.0
– 1.0 –
1.0
Unit
mA
V
V
V
V
µA
µA
(*A) All output pins with no load, System Clock frequency: FSCKO = 24.576MHz, Input word clock frequency: FLRCI = 48kHz, Supply voltage: VDD = 3.3V
Pin type
Note Type
Names
(*1)
Inputs
LRCI, BCKI, DI, TMOD0, RSTN, IISI, IMOD0, IMOD1, DEEM, FS0, FS1, DMUTE, THROU, TMOD1, OMOD1,
OMOD0, IISO, SCKO, SLAVE
(*2)
Output
DOUT
(*3) Inputs/Outputs BCKO, LRCO
Note: All inputs and input/output pins are 5V compatible. Consequently, input voltages up to 5.5V can be connected. However, while input/output pins in
input mode can have input voltage up to 5.5V, input/output pins in output mode have output voltages that do not rise above VDD level. Plus, in out-
put mode, it is prohibited to use external pull-up to raise the voltage above VDD.
NIPPON PRECISION CIRCUITS INC.—5
5 Page 
SM5950AM
System Reset (RSTN)
The SM5950AM must be reset if any of the following conditions occur during normal operation. A reset pulse
is a LOW-level pulse applied to RSTN, although the reset operation actually occurs on the rising edge of the
LOW-level pulse.
I When the power supply is applied
A reset (RSTN = LOW to HIGH) is required when the power supply voltage is applied and after the LRCI,
BCKI, SCKO (and LRCO, BCKO if in slave mode) clocks have stabilized.
I When the LRCI and BCKI clocks are interrupted
This occurs when the sampling frequency is switched, when clocks stop due to a condition in a previous stage,
when the LRCI, BCKI clocks are dynamically switched, or when otherwise the clocks are not continuous.
A reset (RSTN = LOW to HIGH) is required after the LRCI, BCKI clocks have stabilized.
I When the SCKO (and LRCO, BCKO if in slave mode) clocks are interrupted
This occurs when the sampling frequency is switched, when clocks stop due to a condition in a previous stage,
when the SCKO, LRCO, BCKO clocks are dynamically switched, or when otherwise the clocks are not contin-
uous.
A reset (RSTN = LOW to HIGH) is required after the SCKO, LRCO, BCKO clocks have stabilized.
A reset pulse is required under these conditions because the conversion ratio calculated based on such non-con-
tinuous clocks will result in an incorrect conversion ratio, and hence the output data will have incorrect values.
Output state during reset interval
DOUT is tied LOW during the reset interval (refer to section "Direct Mute" for operation after the reset is
released). In master mode, the LRCO and BCKO clocks are also tied LOW.
Direct Mute (DMUTE)
Direct mute ON/OFF
DMUTE
L
H
Function
Audio data output starts from the next output word.
0 data is output from the next output word.
Other mute operations
Direct mute also occurs at system reset.
RSTN
L
H
Function
0 data is output from the next output word.
Computed data output starts after 8 output word cycles.
NIPPON PRECISION CIRCUITS INC.—11
11 Page | ||
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