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PDF K9K1208U0M-YIB0 Data sheet ( Hoja de datos )
| Número de pieza | K9K1208U0M-YIB0 | |
| Descripción | 64M x 8 Bit NAND Flash Memory | |
| Fabricantes | Samsung semiconductor | |
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K9K1208U0M-YCB0, K9K1208U0M-YIB0
Document Title
64M x 8 Bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No History
0.0 1. Initial issue
- The followings are disprepancy items between K9K5608U0M (256Mb
DDP) and K9K1208U0M (512Mb DDP).
Draft Date Remark
June 19th 2000 Preliminary
AC Characteristics
Read Cycle Time (tRC)
Write Cycle Time (tWC)
WE High hold Time (tWH)
Data Hold Time (tDH)
RE High Hold Time (tREH)
K9K5608U0M
Min. 50ns
Min. 50ns
Min. 15ns
Min. 10ns
Min. 15ns
K9K1208U0M
Min. 60ns
Min. 60ns
Min. 25ns
Min. 15ns
Min. 25ns
0.1 1. Changed Input / Output Capacitance
- Input / Output Capacitance (Max.) : 20 pF --> 30pF
- Input Capacitance (Max.) : 20 pF --> 30pF
June 24th 2000 Preliminary
0.2 1. Changed SE pin description
July 17th 2000 Final
- SE is recommended to coupled to GND or Vcc and should not be
toggled during reading or programming.
0.3 1. Changed don’t care mode in address cycles
Nov. 20th 2000
- *X can be "High" or "Low" => *L must be set to "Low"
2. Explain how pointer operation works in detail.
3. Renamed GND input (pin # 6) on behalf of SE (pin # 6)
- The SE input controls the access of the spare area. When SE is high,
the spare area is not accessible for reading or programming. SE is rec
ommended to be coupled to GND or Vcc and should not be toggled
during reading or programming.
=> Connect this input pin to GND or set to static low state unless the
sequential read mode excluding spare area is used.
4. Updated operation for tRST timing
- If reset command(FFh) is written at Ready state, the device goes into
Busy for maximum 5us.
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
1
1 page  
K9K1208U0M-YCB0, K9K1208U0M-YIB0
FLASH MEMORY
PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge
of RE which also increments the internal column address counter by one.
GND (Pin # 6)
Connect this input pin to GND or set to static low state unless the sequential read mode excluding spare area is used.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
5
5 Page 
K9K1208U0M-YCB0, K9K1208U0M-YIB0
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Write D0h
Read Data
Read Status Register
ECC Generation
I/O 6 = 1 ?
or R/B = 1 ?
No
* No
Erase Error
Yes
I/O 0 = 0 ?
Yes
Erase Completed
No
Reclaim the Error
Verify ECC
Yes
Page Read Completed
* : If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
Buffer
memory
error occurs
Page a
Block A
When the error happens with page "a" of Block "A", try
to write the data into another Block "B" from an exter-
nal buffer. Then, prevent further system access to
Block "A" (by creating a "invalid block" table or other
appropriate scheme.)
Block B
11
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| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet K9K1208U0M-YIB0.PDF ] | |
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