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PDF K7R641882M Data sheet ( Hoja de datos )
| Número de pieza | K7R641882M | |
| Descripción | 2Mx36 & 4Mx18 & 8Mx9 QDRTM II b2 SRAM | |
| Fabricantes | Samsung semiconductor | |
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K7R643682M
K7R641882M
K7R640982M
Preliminary
2Mx36 & 4Mx18 & 8Mx9 QDRTM II b2 SRAM
Document Title
2Mx36-bit, 4Mx18-bit, 8Mx9-bit QDRTM II b2 SRAM
Revision History
Rev. No.
History
0.0 1. Initial document.
0.1 1. Update AC timing characteristics.
2. Change the JTAG instruction coding.
0.2 1. Change the AC timing characteristics. (-25/-20 parts)
2. Correct the overshoot and undershoot timing diagrams.
3. Change the JTAG Block diagrams.
4. Update the Boundary scan exit order.
0.3 1. Correct the JTAG ID register definition
2. Correct the AC timing parameter (delete the tKHKH Max value)
0.4 1. Add the Power-on Sequence specification
0.5 1. Correct the pin name table
Draft Date
Sep, 14 2002
Oct. 24, 2002
Remark
Advance
Preliminary
Feb. 18, 2003
Preliminary
Mar. 20, 2003
Preliminary
Aug. 16, 2004
Oct. 18, 2004
Preliminary
Preliminary
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - Oct. 2004
Rev 0.5
1 page  
K7R643682M
K7R641882M
K7R640982M
Preliminary
2Mx36 & 4Mx18 & 8Mx9 QDRTM II b2 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7R640982M(8Mx9)
1 2 3 4 5 6 7 8 9 10 11
A CQ SA SA W NC K NC R SA SA CQ
B NC NC NC SA NC K BW SA NC NC Q3
C NC NC NC VSS SA SA SA VSS NC NC D3
D NC D4 NC VSS VSS VSS VSS VSS NC NC NC
E NC
NC
Q4
VDDQ
VSS
VSS
VSS VDDQ NC
D2
Q2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G NC
D5
Q5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q1
D1
K NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L NC
Q6
D6
VDDQ
VSS
VSS
VSS VDDQ NC
NC
Q0
M NC NC NC VSS VSS VSS VSS VSS NC NC D0
N NC D7 NC VSS SA SA SA VSS NC NC NC
P NC NC Q7 SA SA C SA SA NC D8 Q8
R TDO TCK
SA
SA
SA
C
SA SA SA TMS TDI
Notes: 1. BW controls write to D0:D8 .
PIN NAME
SYMBOL
K, K
C, C
CQ, CQ
Doff
SA
D0-8
Q0-8
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
2A,3A,9A,10A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
11M,11J,10E,11C,2D,2G,3L,2N,10P
11L,10J,11E,11B,3E,3G,2L,3P,11P
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Address Inputs
Data Inputs
Data Outputs
NOTE
1
W
R
BW
VREF
ZQ
VDD
VDDQ
VSS
TMS
TDI
TCK
TDO
NC
4A Write Control Pin,active when low
8A Read Control Pin,active when low
7B Nybble Write Control Pin,active when low
2H,10H
Input Reference Voltage
11H Output Driver Impedance Control Input
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
Power Supply ( 1.8 V )
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply ( 1.5V or 1.8V )
4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
Ground
10R JTAG Test Mode Select
11R JTAG Test Data Input
2R JTAG Test Clock
1R JTAG Test Data Output
7A,5A,1B,2B,3B,5B,9B,10B,1C,2C,3C,9C,10C,1D,3D,9D,10D,
11D,1E,2E,9E,1F,2F,3F,9F,10F,11F,1G,9G,10G,11G,1J,2J,3J,9J
1K,2K,3K,10K,11K,9K,1L,9L,10L,1M,2M,3M,9M,10M,1N,3N,9N
10N,11N,1P,2P,9P
No Connect
2
3
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
- 5 - Oct. 2004
Rev 0.5
5 Page 
K7R643682M
K7R641882M
K7R640982M
Preliminary
2Mx36 & 4Mx18 & 8Mx9 QDRTM II b2 SRAM
AC ELECTRICAL CHARACTERISTICS (VDD=1.8V ±0.1V, TA=0°C to +70°C)
PARAMETER
Input High Voltage
Input Low Voltage
SYMBOL
VIH (AC)
VIL (AC)
MIN
VREF + 0.2
-
MAX
-
VREF - 0.2
Notes: 1. This condition is for AC function test only, not for AC parameter test.
2. To maintain a valid level, the transitioning edge of the input must :
a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC)
b) Reach at least the target AC level
c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
UNIT
V
V
NOTES
1,2
1,2
AC TIMING CHARACTERISTICS(VDD=1.8V±0.1V, TA=0°C to +70°C)
PARAMETER
SYMBOL
Clock
Clock Cycle Time (K, K, C, C)
tKHKH
Clock Phase Jitter (K, K, C, C)
tKC var
Clock High Time (K, K, C, C)
tKHKL
Clock Low Time (K, K, C, C)
tKLKH
Clock to Clock (K↑ → K↑, C↑ → C↑)
tKHKH
Clock to data clock (K↑ → C↑, K↑→ C↑) tKHCH
DLL Lock Time (K, C)
tKC lock
K Static to DLL reset
tKC reset
Output Times
C, C High to Output Valid
tCHQV
C, C High to Output Hold
tCHQX
C, C High to Echo Clock Valid
tCHCQV
C, C High to Echo Clock Hold
tCHCQX
CQ, CQ High to Output Valid
tCQHQV
CQ, CQ High to Output Hold
tCQHQX
C, High to Output High-Z
tCHQZ
C, High to Output Low-Z
tCHQX1
Setup Times
Address valid to K rising edge
tAVKH
Control inputs valid to K rising edge
tIVKH
Data-in valid to K, K rising edge
tDVKH
Hold Times
K rising edge to address hold
tKHAX
K rising edge to control inputs hold
tKHIX
K, K rising edge to data-in hold
tKHDX
-25
MIN MAX
4.00
1.60
1.60
1.80
0.00
1024
30
6.30
0.20
1.80
-0.45
-0.45
-0.30
-0.45
0.45
0.45
0.30
0.45
0.35
0.35
0.35
0.35
0.35
0.35
-20
MIN MAX
5.00
2.00
2.00
2.20
0.00
1024
30
7.88
0.20
2.30
-0.45
-0.45
-0.35
-0.45
0.45
0.45
0.35
0.45
0.40
0.40
0.40
0.40
0.40
0.40
-16
UNITS NOTES
MIN MAX
6.00
2.40
2.40
2.70
0.00
1024
30
8.40
0.20
2.80
ns
ns
ns
ns
ns
ns
cycle
ns
5
6
0.50 ns
-0.50
ns
0.50 ns
-0.50
ns
0.40 ns
-0.40
ns
0.50 ns
-0.50
ns
3
3
7
7
3
3
0.50
0.50
0.50
ns
ns 2
ns
0.50 ns
0.50 ns
0.50 ns
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control singles are R, W,BW0,BW1 and BW2, BW3, also for x36
3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions
(0°C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ± 0.1 ns variation from echo clock to data.
The data sheet parameters reflect tester guardbands and test setup variations.
- 11 -
Oct. 2004
Rev 0.5
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet K7R641882M.PDF ] | |
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