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What is K6X1008C2D-Q?

This electronic component, produced by the manufacturer "Samsung semiconductor", performs the same function as "128Kx8 bit Low Power CMOS Static RAM".


K6X1008C2D-Q Datasheet PDF - Samsung semiconductor

Part Number K6X1008C2D-Q
Description 128Kx8 bit Low Power CMOS Static RAM
Manufacturers Samsung semiconductor 
Logo Samsung semiconductor Logo 


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K6X1008C2D Family
Document Title
128Kx8 bit Low Power CMOS Static RAM
Revision History
Revision No. History
0.0 Initial draft
0.1 Revised
- Deleted 32-TSOP1-0820R Package Type.
- Added Commercial product.
0.2 Revised
- Added Lead Free 32-SOP-525 Product
0.3 Revised
- Added Lead Free 32-TSOP1-0820F Product
1.0 Finalized
- Changed ICC from 10mA to 5mA
- Changed ICC2 from 35mA to 25mA
- Changed ISB from 3mA to 0.4mA
- Changed IDR(industrial) from 15µA to 10µA
- Changed IDR(Automotive) from 25µA to 20µA
CMOS SRAM
Draft Data
July 15, 2002
December 4, 2002
Remark
Preliminary
Preliminary
May 13, 2003
Preliminary
June 21, 2003
Preliminary
September 16, 2003 Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
1 Revision 1.0
September 2003

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K6X1008C2D-Q equivalent
K6X1008C2D Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): CL=100pF+1TTL
CL=50pF+1TTL
CL1)
1. Including scope and jig capacitance
AC CHARACTERISTICS
(VCC=4.5~5.5V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C, Automotive product: TA=-40~125°C)
Parameter List
Read
Write
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Select to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
tRC
tAA
tCO
tOE
tLZ
tOLZ
tHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
Speed Bins
55ns
70ns
Min Max Min Max
55 - 70 -
- 55 - 70
- 55 - 70
- 25 - 35
10 - 10 -
5-5-
0 20 0 25
0 20 0 25
10 - 10 -
55 - 70 -
45 - 60 -
0-0-
45 - 60 -
40 - 50 -
0-0-
0 20 0 25
20 - 25 -
0-0-
5-5-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
Test Condition
Min Typ Max Unit
VDR CS1Vcc-0.2V1)
IDR Vcc=3.0V, CS1Vcc-0.2V1)
2.0 - 5.5 V
K6X1008C2D-B -
- 10 µA
K6X1008C2D-F -
- 10 µA
K6X1008C2D-Q -
- 20 µA
tSDR
tRDR
See data retention waveform
0 - - ms
5- -
1. CS1Vcc-0.2V, CS2VCC-0.2V, or CS20.2V
5 Revision 1.0
September 2003


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