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PDF K4S561632D Data sheet ( Hoja de datos )
| Número de pieza | K4S561632D | |
| Descripción | 256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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K4S561632D
CMOS SDRAM
256Mbit SDRAM
4M x 16bit x 4 Banks
Synchronous DRAM
LVTTL
DataSheet4U.com
DataShee
Revision 0.1
Aug. 2002
DataSheet4U.com
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.1 Aug. 2002
DataSheet4U.com
1 page  
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K4S561632D
CMOS SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
VIN, V OUT
VDD, VDDQ
T STG
PD
IOS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Unit
V
V
°C
W
mA
et4U.com
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -0 to 70°C)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Symbol
VDD , VDDQ
VIH
VIL
VO H
VOL
ILI
Min Typ
3.0 3.3
2.0 3.0
-0.3 0
2.4 -
D-ataSheet4U.c- om
-10 -
Max
3.6
V DD+0.3
0.8
-
0.4
10
Unit
V
V
V
V
V
uA
Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ .
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. The VDD condition of K4S561632C-60 is 3.135V~3.6V.
Note
4
1
2
IOH = -2mA
IOL = 2mA
3
DataShee
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
Pin
Clock
RAS , CAS, WE, CS, CKE, DQM
Address
D Q 0 ~ DQ 15
Symbol
CCLK
C IN
CADD
COUT
Min
2.5
2.5
2.5
4.0
Notes : 1. -75/7C only specify a maximum value of 3.5pF
2. -75/7C only specify a maximum value of 3.8pF
3. -75/7C only specify a maximum value of 6.0pF
Max
4.0
5.0
5.0
6.5
Unit
pF
pF
pF
pF
Note
1
2
2
3
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Rev. 0.1 Aug. 2002
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5 Page 
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K4S561632D
CMOS SDRAM
et4U.com
SIMPLIFIED TRUTH TABLE
Command
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP
A11,A12,
A9 ~ A0
Note
Register
Mode register set
H X LL LLX
OP code
1,2
Refresh
Auto refresh
H
H
LL
LHX
Entry
L
Self
refresh
Exit
LH HH
LH
X
HX X X
3
X
3
3
X
3
Bank active & row addr.
H
X LL HHX V
Row address
Read &
column address
Auto precharge disable
Auto precharge enable
H
X LH LHX V
L
Column
4
address
H
(A0 ~ A8 )
4,5
Write &
column address
Auto precharge disable
Auto precharge enable
H
X LH L LX V
L
Column
4
address
H
(A0 ~ A8 )
4,5
Burst stop
H X LH H LX
X6
Precharge
Bank selection
All banks
VL
H X LLHLX
XH
X
Clock suspend or
active power down
HX X X
Entry H L
X
LV VV
Exit L H X X X X X
X
Precharge power down mode
Entry
Exit
HX X X
HL
X
DataSheLet4UH.com H H
HX X X
LH
X
LV VV
X
DQM
H X V X7
No operation command
HX X X
HX
X
LH HH
X
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes : 1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA 1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA 1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA 0 and BA 1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 0.1 Aug. 2002
DataSheet4U.com
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11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet K4S561632D.PDF ] | |
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