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Número de pieza | K4S511632B-TCL75 | |
Descripción | 512Mb B-die SDRAM Specification | |
Fabricantes | Samsung semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de K4S511632B-TCL75 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
No Preview Available ! SDRAM 512Mb B-die (x4, x8, x16)
CMOS SDRAM
512Mb B-die SDRAM Specification
Revision 1.1
February 2004
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.1 February 2004
1 page SDRAM 512Mb B-die (x4, x8, x16)
FUNCTIONAL BLOCK DIAGRAM
CMOS SDRAM
Data Input Register
Bank Select
CLK
ADD
32Mx4 / 16Mx8 / 8Mx16
32Mx4 / 16Mx8 / 8Mx16
32Mx4 / 16Mx8 / 8Mx16
32Mx4 / 16Mx8 / 8Mx16
Column Decoder
LCKE
LRAS LCBR
LWE
LCAS
Latency & Burst Length
Programming Register
LWCBR
Timing Register
LWE
LDQM
DQi
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.1 February 2004
5 Page SDRAM 512Mb B-die (x4, x8, x16)
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
Output
870Ω
3.3V
1200Ω
50pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
CMOS SDRAM
Unit
V
V
ns
V
Z0 = 50Ω
Vtt = 1.4V
50Ω
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
Col. address to col. address delay
Number of valid output data
tCCD(min)
CAS latency = 3
CAS latency = 2
Version
75
15
20
20
45
100
65
2
2 CLK + tRP
1
1
1
2
1
Unit
ns
ns
ns
ns
us
ns
CLK
ns
CLK
CLK
CLK
ea
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Note
1
1
1
1
1
2
2
2
3
4
Rev. 1.1 February 2004
11 Page |
Páginas | Total 15 Páginas | |
PDF Descargar | [ Datasheet K4S511632B-TCL75.PDF ] |
Número de pieza | Descripción | Fabricantes |
K4S511632B-TCL75 | 512Mb B-die SDRAM Specification | Samsung semiconductor |
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