|
|
PDF K4R271669E Data sheet ( Hoja de datos )
| Número de pieza | K4R271669E | |
| Descripción | 128Mbit RDRAM(E-die) | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de K4R271669E (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
K4R271669E
Direct RDRAM™
128Mbit RDRAM(E-die)
256K x 16 bit x 32s Banks
Direct RDRAMTM
Version 1.4
July 2002
Page -1
Version 1.4 July 2002
1 page  
K4R271669E
Direct RDRAM™
Table 2: Pin Description
Signal
SIO1,SIO0
I/O Type
I/O CMOSa
CMD
I CMOSa
SCK
VDD
VDDa
VCMOS
GND
GNDa
DQA7..DQA0
I CMOSa
I/O RSLb
CFM
I RSLb
CFMN
VREF
CTMN
I RSLb
I RSLb
CTM
I RSLb
RQ7..RQ5 or
ROW2..ROW0
I
RSLb
RQ4..RQ0 or
COL4..COL0
I
RSLb
DQB7..
DQB0
I/O RSLb
NC
Total pin count per package
# Pins
center
2
1
1
6
1
2
9
1
8
1
1
1
1
1
3
5
8
2
54
Description
Serial input/output. Pins for reading from and writing to the control regis-
ters using a serial access protocol. Also used for power management.
Command input. Pins used in conjunction with SIO0 and SIO1 for reading
from and writing to the control registers. Also used for power manage-
ment.
Serial clock input. Clock source used for reading from and writing to the
control registers
Supply voltage for the RDRAM core and interface logic.
Supply voltage for the RDRAM analog circuitry.
Supply voltage for CMOS input/output pins.
Ground reference for RDRAM core and interface.
Ground reference for RDRAM analog circuitry.
Data byte A. Eight pins which carry a byte of read or write data between
the Channel and the RDRAM device.
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Positive polarity.
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Negative polarity
Logic threshold reference voltage for RSL signals
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Negative polarity.
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Positive polarity.
Row access control. Three pins containing control and address informa-
tion for row accesses.
Column access control. Five pins containing control and address informa-
tion for column accesses.
Data byte B.Eight pins which carry a byte of read or write data between
the Channel and the RDRAM device.
No Connection.
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
Page 3 Version 1.4 July 2002
5 Page 
K4R271669E
Direct RDRAM™
Table 7 shows the COP field encoding. The device must be
in the ATTN power state in order to receive COLC packets.
The COLC packet is used primarily to specify RD (read) and
WR (write) commands. Retire operations (moving data from
the write buffer to a sense amp) happen automatically. See
Figure 18 for a more detailed description.
The COLC packet can also specify a PREC command,
which precharges a bank and its associated sense amps. The
RDA/WRA commands are equivalent to combining RD/WR
with a PREC. RLXC (relax) performs a power mode transi-
tion. See “Power State Management” on page 50.
Table 7: COLC Packet Field Encodings
S
DC4.. DC0
(select device)a
COP3..0
Name
Command Description
0 ----
1 /= (DEVID4 ..0)
1 == (DEVID4 ..0)
1 == (DEVID4 ..0)
1 == (DEVID4 ..0)
1 == (DEVID4 ..0)
1 == (DEVID4 ..0)
1 == (DEVID4 ..0)
1 == (DEVID4 ..0)
1 == (DEVID4 ..0)
1 == (DEVID4 ..0)
-----
-----
x000b
x001
x010
x011
x100
x101
x110
x111
1xxx
- No operation.
- Retire write buffer of this device.
NOCOP Retire write buffer of this device.
WR Retire write buffer of this device, then write column C5..C0 of bank BC4..BC0 to write buffer.
RSRV Reserved, no operation.
RD Read column C5..C0 of bank BC4..BC0 of this device.
PREC Retire write buffer of this device, then precharge bank BC4..BC0 (see Figure 15).
WRA Same as WR, but precharge bank BC4..BC0 after write buffer (with new data) is retired.
RSRV Reserved, no operation.
RDA Same as RD, but precharge bank BC4..BC0 afterward.
RLXC Move this device into the standby (STBY) power state (see Figure 48).
a. “/=” means not equal, “==” means equal.
b. An “x” entry indicates which commands may be combined. For instance, the two commands WR/RLXC may be specified in one COP value (1001).
Table 8 shows the COLM and COLX field encodings. The
M bit is asserted to specify a COLM packet with two 8 bit
bytemask fields MA and MB. If the M bit is not asserted, an
COLX is specified. It has device and bank address fields,
and an opcode field. The primary use of the COLX packet is
to permit an independent PREX (precharge) command to be
specified without consuming control bandwidth on the ROW
pins. It is also used for the CAL(calibrate) and SAM
(sample) current control commands (see “Current and
Temperature Control” on page 56), and for the RLXX power
mode command (see “Power State Management” on page
50).
Table 8: COLM Packet and COLX Packet Field Encodings
M
DX4 .. DX0
(selects device)
XOP4..0
Name
1 ----
0 /= (DEVID4 ..0)
0 == (DEVID4 ..0)
0 == (DEVID4 ..0)
0 == (DEVID4 ..0)
0 == (DEVID4 ..0)
0 == (DEVID4 ..0)
0 == (DEVID4 ..0)
-
-
00000
1xxx0a
x10x0
x11x0
xxx10
xxxx1
MSK
-
NOXOP
PREX
CAL
CAL/SAM
RLXX
RSRV
Command Description
MB/MA bytemasks used by WR/WRA.
No operation.
No operation.
Precharge bank BX4..BX0 of this device (see Figure 15).
Calibrate (drive) IOL current for this device (see Figure 54).
Calibrate (drive) and Sample ( update) IOL current for this device (see Figure 54).
Move this device into the standby (STBY) power state (see Figure 48).
Reserved, no operation.
a. An “x” entry indicates which commands may be combined. For instance, the two commands PREX/RLXX may be specified in one XOP value (10010).
Page 9 Version 1.4 July 2002
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet K4R271669E.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| K4R271669A | 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM | Samsung semiconductor |
| K4R271669A-NbMCcG6 | 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM | Samsung semiconductor |
| K4R271669A-NMCK7 | 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM | Samsung semiconductor |
| K4R271669A-NMCK8 | 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM | Samsung semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |