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PDF S5T8809X01-R0B0 Data sheet ( Hoja de datos )
| Número de pieza | S5T8809X01-R0B0 | |
| Descripción | PLL FREQUENCY SYNTHESIZER FOR PAGER | |
| Fabricantes | Samsung semiconductor | |
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PLL FREQUENCY SYNTHESIZER FOR PAGER
S5T8809
INTRODUCTION
S5T8809 is a superior low-power-programmable PLL frequency
synthesizer which can be used in high performance / Simple
application for a Wide Area Pager system.
S5T8809 consists of 2 kinds of divider block including a 19-bit Shift
register, 16/18-bit Latch, 13/15bits R-counter and 16/18-bit N-
Counter, 32/33 Prescaler, and a phase detector block including a
Phase detector, Lock detector and a Charge pump.
S5T8809 also has a battery saving mode which can control each
register block by serial control data from the µ-controller (MICOM)
and it also has boost up signal output for fast locking.
16-TSSOP-0044
( Magnification = 1 : 4 )
FEATURES
• Maximum operating frequency: 330MHz @ 300mVP-P, VDD1 = 1.0V, VDD2 = 3.0V
• On-chip reference oscillator supports external crystal which oscillates up to 23MHz
• Superior supply current:
— FFIN = 310MHz, IDD1 = 0.8mA (Typ.) @ VDD1 = 1.0V, VDD2 = 3.0V
• Operating voltage: VDD1 = 0.95 to 1.5V and VDD2 = 2.0 to 3.3V
• Excellent Divider range:
— Ref. Divider:
FRC (0): 1 / 40 to 1 / 65528 (Multiple): Default
FRC (1): 1 / 5 to 1 / 32767
— Rx Divider:
PBC (0): 1 / 1056 ~ 1 / 65535: Default
PBC (1): 1 / 1056 ~ 1 / 262143
• Boost-up signal output for Fast Locking
• In the Standby mode, VDD1 block can be controlled by BSB Pin status
— Standby current consumption: 10µA (Max.)
• Programmable control the output of LD to reduce internal noise
• Programmable 17 / 19-bit shift register value controlled by PBC
• Charge pump output circuitry for passive filter
• Package type: 16−TSSOP (0.65mm)
ORDERING INFORMATION
Device
+S5T8809X01-R0B0
+: New Product
Package
16−TSSOP−0044
Operating Temperature
−25°C to +75°C
1
1 page  
PLL FREQUENCY SYNTHESIZER FOR PAGER
S5T8809
ABSOLUTE MAXIMUM RATINGS
Characteristic
Supply Voltage
Input Voltage
Power Dissipation
Operating Temperature
Storage Temperature
Symbol
VDD ~ VDD2
VI
PD
TOPR
TSTG
Value
−0.3 ~ +4.0
VSS −0.3 ~ VDD + 0.3
350
−25 ~ +75
−40 ~ +125
Unit
V
V
mW
°C
°C
ELECTRICAL CHARACTERISTICS
(Ta = 25°C, VDD1 = 1.0V, VDD2 = 3.0V, unless otherwise specified)
Characteristic
Operating voltage
Operating current
Standby current
Input voltage
(DATA, CLK, EN, BS)
Input voltage
(TEST, PBC)
Input current
(Fin, Xin)
Input frequency
Output current
(PDO, FL)
Output current
(LD)
Setup-time
(DATA-CLK, CLK-EN)
Hold time
Symbol
Test Conditions
VDD1
VDD2
IDD
ISB1
VIL
VIH
VIL
VIH
IIH
IIL
FFIN
FOSCI
IOH1
IOL1
IOH2
IOL2
ts
−
−
FOSCI = 12.8MHz
FFIN = 310MHz @ 0.3VP-P
VDD1 = 1.0V, VDD2 = 3.0V, BSB=High
VDD1 = 0.0V, VDD2 = 3.0V, BSB=Low
−
−
−
−
VIH = VDD1, BSB = High
VIL = 0V, BSB = High
VFIN = 0.3VP-P, VDD1 = 1.0V
VOSCI = 0.3VP-P, VDD1 = 1.0V
VOH = 0.4V
VOL = VDD2 - 0.4V
VOH = 0.4V
VOL = VDD2 - 0.4V
−
Min.
0.95
2.0
−
Typ.
1.0
3.0
0.8
−
−
VDD2-0.3
−
VSS1-0.2
−
−
40
7
1.0
1.0
0.1
0.1
2
0.1
−
−
−
−
−
−
−
12.8
−
−
−
−
−
Max.
1.5
3.3
−
10
0.3
−
0.2
−
20
20
330
23
−
−
−
−
−
Unit
V
mA
µA
V
V
µA
MHz
mA
mA
µS
tH − 2 − − µS
5
5 Page 
PLL FREQUENCY SYNTHESIZER FOR PAGER
PHASE DETECTOR / LOCK DETECTOR
OSCI 1
OSCO 2
LD 10
Fin 7
1/ 8
CNT
13 or 15 Bit
R- Divider
Lock
Detector
FRC
Fr
Fn
Phase
Detector
32/33
Counter
16 or 18 Bit
N- Divider
FLC
Figure 5. Phase Detector / Lock Detector
S5T8809
5 PDO
4 FL
9 PBC
Fr
Fn
PDO Z-State
LD
GND
VDD1
FL Z-State
* Fast Lock Operation Window
Window width = OSCI x 4
Figure 6. Figure 5-2. Phase Detector / Lock Detector / Fast Lock Output Waveforms
NOTES:
1. Phase detector always compares the Phase difference of N-counter with R-counter, and generates High or Low
State as much as the phase difference
2. The LD output is set to Low level same as Phase detector error width
11
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