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PDF S5L9290X01-L0R0 Data sheet ( Hoja de datos )

Número de pieza S5L9290X01-L0R0
Descripción signal processing LSI for the CD
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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No Preview Available ! S5L9290X01-L0R0 Hoja de datos, Descripción, Manual

DIGITAL SIGNAL PROCESSOR FOR CDP
PRELIMINARY
S5L9290X
INTRODUCTION
S5L9290X is a signal processing LSI for the CD. Digital processing function
(EFM demodulation, error correction), spindle motor servo processing, wide
capture range DPLL and 1-bit DAC for the CD player are installed in
S5L9290X.
48-LQFP-0707
FEATURES
• Signal processing part
— EFM data demodulation
— Frame sync detection, protection, insertion
— Sub code data processing (Q data CRC check, Q data register installed)
— Error correction (C1: 2 error correction, C2: 4 erasure correction)
— Installed 16K SRAM for De-interleave
— Interpolation
— Digital audio interface
— CLV servo control (X1, X2)
— Wide capture range digital PLL ( ± 50%)
• Digital filter, DAC part
— 4 times over sampling digital filter
— Digital de-emphasis (can be process the 32kHz, 44.1kHz, 48kHz)
— Sigma-delta stereo DAC installed
— Audio L.P.F installed
ORDERING INFORMATION
Device
S5L9290X01L0R0
Package
48-LQFP-0707
Supply Voltage
2.7V 3.3V (Analog, Internal logic)
2.7V 5.5V (I/O port)
Operating Temperature
-20°C +75°C
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S5L9290X01-L0R0 pdf
DIGITAL SIGNAL PROCESSOR FOR CDP
NO. NAME
25 SQDT
26 MUTE
27 VDDD2-3V
28 VSSD2
28 VDDD3-5V
30 SBCK
31 JITB
32 C2PO
33 DATX
34 SADTO
35 LRCKO
36 BCKO
37 BCKI
38 LRCKI
39 SADTI
40 VSSD_DAC
41 VDDD_DAC
42 RCHOUT
43 VSSA_DAC
44 VREF
45 VHALF
46 VDDA_DAC
47 LCHOUT
48 VDDA_PLL
Table 1. Pin Description (continued)
I/O Function Description
O Subcode-Q data serial output
I System mute at 'H'
- Digital Power (3V Power, Internal Logic)
- Digital Ground (Internal Logic)
- Digital Power (5V Power, I/O PAD)
I Subcode data transfering bit clock
O Internal SRAM jitter margin status output
O C2 pointer output
O Digital audio data output
O Serial audio data output (48 slot, MSB first)
O Channel clock output
O Bit clock output
I Bit clock input
I Channel clock input
I Serial audio data input (48 slot, MSB first)
- Digital Ground for DAC
- Digital Power for DAC (3V Power)
O Right-Channel audio output through DAC
- Analog Ground for DAC
O Referance Voltage output for bypass
O Referance Voltage output for bypass
- Analog Power for DAC (3V Power)
O Left-Channel audio output through DAC
- Analog Power for PLL (3V Power)
PRELIMINARY
S5L9290X
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S5L9290X01-L0R0 arduino
DIGITAL SIGNAL PROCESSOR FOR CDP
PRELIMINARY
S5L9290X
Command
1-bit DAC &
DATX control
1-bit DAC
attenuation
control
Output port
control
SADT I/F
control
Play mode
control
TEST mode
control
Address
10100011
($A3)
10100100
($A4)
10101001
($A9)
10110000
($B0)
11110000
($F0)
11111111
($FF)
D7
M5
-
DS1
D6 D5
TXSF [3:0]
M4 M3
TALK [3:0]
--
DS0 -
TEST [3:0]
Data
D4 D3 D2
SC[3:0]
D1 D0
SPLFREQ[1:0]
ISTAT
pin
Hi-Z
M2
M1
M0 SOFT CMD
Hi-Z
ATTN DIRECT
- - - - Hi-Z
-
-
-
-
MSON
Hi-Z
- - DFCK - - Hi-Z
- - - - Hi-Z
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