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PDF S5H1420 Data sheet ( Hoja de datos )
| Número de pieza | S5H1420 | |
| Descripción | Channel Decoder for DVB-S/DSS | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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[Channel Lab]
S5H1420
[Channel Decoder for DVB-S/DSS]
DATA SHEET
Samsung Electronics Co, Ltd.
10 Jan. 2004
(Version 4.5.1)
Note: This documentation is preliminary and is subject to change. Samsung Electronics Co, Ltd.
reserves the right to do any kind of modification in this data sheet regarding hardware or
software implementations without notice.
Samsung Electronics Co, Ltd. Proprietary Information
-1-
1 page  
2.2 Pin descriptions
Pin Name
I/O Cell Type
OLF
RESET_N
ERROR
SYNC
VALID
NC
DATA
DATA
Input
Schmitt Trigger
Error_out
Sync_out
Valid_out
NC
Output [7]
Output [7:0]
SDA
I/O-open drain(5V)
SCL
Input(5V)
CLK_SEL
Input
ID_SEL0
Input
ID_SEL1
Input
TEST_SEL0
Input
TEST_SEL1
Input
NC NC
XTAL_IN
Oscillator Input
XTAL_OUT
Oscillator Output
FMHZCLKOUT
Output
RFSDA
I/O-open drain (5V)
RFSCL
n-ch-open drain (5V)
ADC_OSC_IN
Oscillator Input
AVDD_ADC
Digital Power
IP Inphase Positive
IN Inphase Negative
QN Quadrature Negative
QP Quadrature Positive
VREF_L
Analog Reference
VREF_H
Analog Reference
CML
Analog Reference
AGC
n-ch Open Drain(5V)
DISEQC
Bidirectional (5V)
BYTE_CLOCK
Output (3.3V)
VSEL
Output
LNB_EN
Output
RF Interface & ADC Power Supply (24)
ADC
PLL
IO
Logic
AVDD_ADC
AVSS_ADC
AVBB_ADC
AVDD_PLL
AVSS_PLL
AVBB_PLL
AVDD_PLL
AVSS_PLL
VSS33
VDD33
VSS25
VDD25
S5H1420
DBS Channel Decoder for DVB-S/DSS
Pin Number
1
2
3
4
5
6
30
[:]
21
22
23
24
24
28
29
18
36
37
38
41
42
45
46
47
48
50
51
53
54
55
60
61
62
63
64
Description
LNB Over Load Flag
H/W Reset (Active Low)
Error indicator output
Synchronization output
Valid data period
NC
MPEG2 Stream Serial Data
MPEG2 Stream Parallel Data
[Pin 30,17,16,15,12,11,10,9]
Serial Data from host
Serial Clock from host
Master Clock Select
I2C Address Select[T0]
I2C Address Select[T1]
Test Mode Select[T2]
Test Mode Select[T3]
No connection
Crystal Oscillator Input
Crystal Oscillator Output
Reference Clock Output
RF Module Control SDA
RF Module Control SCL
Oscillator Input
ADC Total Power
ADC Analog Input
ADC Analog Input
ADC Analog Input
ADC Analog Input
ADC Bottom Reference Voltage
ADC Top Reference Voltage
Common Mode Level Voltage
Gain Control Output
Antenna Select
Data Transfer clock
LNB Voltage Select Flag
LNB Enable Flag
46, 57
56, 49
52
31
32
33
34
35
13, 39
14, 40
7, 19, 26, 43, 58
8, 20, 27, 44, 59
Samsung Electronics Co, Ltd. Proprietary Information
-5 -
5 Page 
Figure4 : Parallel output interface
BYTE_CLOCK
MPEG_CLK=1
CDCLK_POL=1
MPEG_CLK=0
CDCLK_POL=0
VALID
MPEG_CLK=1
MPEG_CLK=0
SYNC
ERROR
MPEG_ERR=1
MPEG_ERR=0
S5H1420
DBS Channel Decoder for DVB-S/DSS
No Error
Data
Uncorrectible Packet
Parity
No Error
Figure5 : Serial output interface
SYNC
BYTE_CLOCK
CDCLK_POL=1
CDCLK_POL=0
VALID
MPEG_DOUT=1
D0
MPEG_DOUT=0
ERROR
MPEG_ERR=1
MPEG_ERR=0
1/fclk
DATA
First bit of the packet
Useful Data
1 packet
Parity
Parity
Table 0
Parallel
Serial
Bit1 of 0x39
SER_PAR
0
1
Bit4 of 0x02
SER_SEL_MODE
1
1
MPEG Data
DATA [7:0]
DATA[7]
MPEG Clock
BYTE_CLK
BYTE_CLK
Samsung Electronics Co, Ltd. Proprietary Information
- 11 -
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet S5H1420.PDF ] | |
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