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PDF S3C4530A Data sheet ( Hoja de datos )
| Número de pieza | S3C4530A | |
| Descripción | 16/32-bit RISC microcontroller is a cost-effective/ high-performance microcontroller | |
| Fabricantes | Samsung semiconductor | |
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S3C4530A
PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
INTRODUCTION
Samsung's S3C4530A 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller
solution for Ethernet-based systems. An integrated Ethernet controller, the S3C4530A, is designed for use in
managed communication hubs and routers.
The S3C4530A is built around an outstanding CPU core: the 16/32-bit ARM7TDMI RISC processor designed by
Advanced RISC Machines, Ltd. The ARM7TDMI core is a low-power, general purpose microprocessor macro-cell
that was developed for use in application-specific and custom-specific integrated circuits. Its simple, elegant, and
fully static design is particularly suitable for cost-sensitive and power-sensitive applications.
The S3C4530A offers a configurable 8-Kbyte unified cache/SRAM and Ethernet controller which reduces total
system cost. Most of the on-chip function blocks have been designed using an HDL synthesizer and the
S3C4530A has been fully verified in Samsung's state-of-the-art ASIC test environment.
Important peripheral functions include two HDLC channels with buffer descriptor, two UART channels with full
modem interface signal and 32byte buffer, 2-channel GDMA, two 32-bit timers, and 26 programmable I/O ports.
On-board logic includes an interrupt controller, DRAM/ SDRAM controller, and a controller for ROM/SRAM and
flash memory. The System Manager includes an internal 32-bit system bus arbiter and an external memory
controller.
The following integrated on-chip functions are described in detail in this user's manual:
— 8-Kbyte unified cache/SRAM
— I2C interface
— Ethernet controller
— HDLC controller
— GDMA
— UART
— Timers
— Programmable I/O ports
— Interrupt controller
1-1
1 page  
S3C4530A
PRODUCT OVERVIEW
VDD
VSS
nUADSR1/P<23>
UATXD1/P<24>
nUADTR1/P<25>
nDTRA
RXDA
nRTSA
TXDA
nCTSA
VDD
VSS
nDCDA
RXCA
nSYNCA
TXCA
nDTRB
RxDB
nRTSB
TXDB
VDD
VSS
nCTSB
nDCDB
RXCB
nSYNCB
TXCB
CRS/CRS_ 10M
RX DV/LINK_10M
RXD<0>/RXD_10M
VDD
VSS
RXD<1>
RXD<2>
RXD<3>
RX ERR
RX_CLK/RXCLK_10M
COL/COL_10M
TXD<0>/TXD_10M
TXD<1>/LOOP_10M
VDD
VSS
TXD<2>
TXD<3>
Tx_ERR/POCMP_10M
TXCLK/TXCLK_10M
TX_EN/TXEN_10M
MDIO
LITTLE
MDC
VDD
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
S3C4530A
(208-QFP)
156 VSS
155 VDD
154 XDATA<16>
153 XDATA<15>
152 XDATA<14>
151 XDATA<13>
150 XDATA<12>
149 XDATA<11>
148 XDATA<10>
147 XDATA<9>
146 XDATA<8>
145 XDATA<7>
144 XDATA<6>
143 VSS
142 VDD
141 XDATA<5>
140 XDATA<4>
139 XDATA<3>
138 XDATA<2>
137 XDATA<1>
136 XDATA<0>
135 ADDR<21>
134 ADDR<20>
133 ADDR<19>
132 ADDR<18>
131 VSS
130 VDD
129 ADDR<17>
128 ADDR<16>
127 ADDR<15>
126 ADDR<14>
125 ADDR<13>
124 ADDR<12>
123 ADDR<11>
122 ADDR<10>/AP
121 ADDR<9>
120 ADDR<8>
119 VSS
118 VDD
117 ADDR<7>
116 ADDR<6>
115 ADDR<5>
114 ADDR<4>
113 ADDR<3>
112 ADDR<2>
111 ADDR<1>
110 ADDR<0>
109 ExtMACK
108 ExtMREQ
107 nWBE<3>/DQM<3>
106 VSS
105 VDD
Figure 1-2. S3C4530A Pin Assignment Diagram
1-5
5 Page 
S3C4530A
PRODUCT OVERVIEW
Signal
RXCA
TXCA
TXDB
RXDB
nDTRB
nRTSB
nCTSB
nDCDB
nSYNCB
RXCB
TXCB
UCLK
UARXD0/P[18]
UATXD0/P[20]
nUADSR0/P[19]
nUADTR0/P[21]
Table 1-1. S3C4530A Signal Descriptions (Continued)
Pin No.
14
16
20
18
17
19
23
24
26
25
27
64
202
204
203
205
Type
I
I/O
O
I
O
O
I
I
O
I
I/O
I
I/B
O/B
I/B
O/B
Description
HDLC Ch-A Receiver Clock. When this clock input is used as the
receiver clock, the receiver samples the data on the positive
edge of RXCA clock. It is possible to samples the data on the
negative edge by register setting. This clock can be the source
clock of the receiver, the baud rate generator, or the DPLL.
HDLC Ch-A Transmitter Clock. When this clock input is used as
the transmitter clock, the transmitter shifts data on the negative
transition of the TXCA clock . It is possible to samples the data
on the positive edge by register setting. If you do not use TXCA
as the transmitter clock, you can use it as an output pin for
monitoring internal clocks such as the transmitter clock, receiver
clock, and baud rate generator output clocks.
HDLC Ch-B Transmit Data. See the TXDA pin description.
HDLC Ch-B Receive Data. See the RXDA pin description.
HDLC Ch-B Data Terminal Ready. See the nDTRA pin
description.
HDLC Ch-B Request To Send. See the nRTSA pin description.
HDLC Ch-B Clear To Send. See the nCTSA pin description.
HDLC Ch-B Data Carrier Detected. See the nDCDA pin
description.
HDLC Ch-B Sync is detected. See the nSYNCA pin description.
HDLC Ch-B Receiver Clock. See the RXCA pin description.
HDLC Ch-B Transmitter Clock. See the TXCA pin description.
The external UART clock input. MCLK or PLL generated clock
can be used as the UART clock. You can use UCLK, with an
appropriate divided by factor, if a very precious baud rate clock is
required.
UART0 Receive Data. RXD0 is the UART0 input signal for
receiving serial data. This pin can be used general I/O port also.
It can be controlled by IOPCON register. See chapter 12.
UART0 Transmit Data. TXD0 is the UART0 output signal for
transmitting serial data. This pin can be used general I/O port
also. It can be controlled by IOPCON register. See chapter 12.
Not UART0 Data Set Ready. This input signals in the UART0 that
the peripheral (or host) is ready to transmit or receive serial data.
See chapter 10.
Not UART0 Data Terminal Ready. This output signals the host
(or peripheral) that UART0 is ready to transmit or receive serial
data. This pin output state can be controlled by UART0 control
register.
1-11
11 Page | ||
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| PDF Descargar | [ Datasheet S3C4530A.PDF ] | |
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