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PDF S3C2510A Data sheet ( Hoja de datos )
| Número de pieza | S3C2510A | |
| Descripción | 16/32-bit RISC micro-controller is a cost-effective/ high-performance micro-controller solution for Ethernet-based systems/ for example | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de S3C2510A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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S3C2510A
1 PRODUCT OVERVIEW
PRODUCT OVERVIEW
1.1 OVERVIEW
Samsung's S3C2510A 16/32-bit RISC micro-controller is a cost-effective, high-performance micro-controller
solution for Ethernet-based systems, for example, SOHO router, internet gateway, WLAN AP, etc.
To efficiently support those network applications, S3C2510A provides the followings: 16/32-bit ARM940T RISC
embedded with 4K-byte I-cache and 4K-byte D-cache, memory controller with 24-bit external address pins, one
external bus master with bus request/acknowledge pins, two 10/100 Mbps Ethernet controllers, PCI & PC Card
host/agent controller, AAL5 SAR and UTOPIA L1/L2, two port full/low speed USB host with root hub, one port
USB function device with transceiver, six general-purpose DMAs, two high-speed UARTs, one console UART,
DES and 3DES for IP security, IIC serial interface, interrupt controller, six 32-bit programmable timers, 30-bit
watchdog timer, 64 programmable I/O ports, and four PLLs for clock generation.
The S3C2510A is developed using an ARM940T core, 0.18um CMOS standard cells and a memory compiler. Its
powerful, elegant and fully static design is suitable for various network applications. Also S3C2510A adopts a new
bus architecture, AMBA (Advanced Microcontroller Bus Architecture).
1-1
1 page  
S3C2510A
PRODUCT OVERVIEW
PCI & PC Card Host/Agent Controller
S3C2510A's PCI & PC Card Host/Agent Controller complies with the PCI Local Bus Specification rev. 2.2, PC
Card Standard Release 7.2, and various design guides. PCI & PC Card Controller connects the ARM940T
processor core and local system memory to the PCI bus or CardBus socket. The PCI bus or CardBus uses a 32-
bit multiplexed, address/data bus, and various control and error signals. Mis-aligned transfers are supported as
well as burst transfers at the maximum data rate of 264MB/s @66MHz (132MB/s @33MHz). S3C2510A can
function as a PCI(or CardBus) master(initiator) or target(slave), and function as PCI host bridge(or CardBus host
bus adapter) referred to as "host mode" or PCI device(or CardBus PC Card) referred to as "agent mode". In host
mode, it can be used as host/PCI bridge (or CardBus socket controller) on main board . But in agent mode, it can
be used as PCI device on PCI card or CardBus device on CardBus PC Card. The PCI & PC Card Host Controller
provides PCI bus arbitration for the S3C2510A and up to five other PCI bus masters (except PCI target-only
devices). It can be disabled to allow for external PCI arbiter (if more than five PCI bus masters will be connected).
The PCI & PC Card Host Controller has one integrated block for PCI interface and CardBus interface (common
silicon) and it supports only one interface as defined by PCI_PCCDM(PC Card Mode) pin. And PCI_HOSTM pin
signal forces PCI & PC Card Controller to operate in host mode or agent mode. Each modes can be set as
followings.
PCI Host Mode
PCI Agent Mode
CardBus PC Card Host Mode
16-bit PC Card (PCMCIA) Host Mode
CardBus PC Card Agent Mode
PCI_PCCDM = 0, PCI_HOSTM=1
PCI_PCCDM = 0, PCI_HOSTM=0
PCI_PCCDM = 1, PCI_HOSTM=1, CardBus PC Card is inserted
PCI_PCCDM = 1, PCI_HOSTM=1, 16-bit PC Card is inserted
PCI_PCCDM = 1, PCI_HOSTM=0
NOTE: Each mode is selected by PCI_PCCDM & PCI_HOSTM pin input and inserted card type
The PCI & PC Card Host/Agent Controller provides an address translation mechanism to map inbound PCI to local
memory or peripherals and outbound processor core or peripherals to PCI. Four independent 8-word deep FIFOs
are implemented for flow-through operation of PCI & PC Card read/write burst operation. And doorbell and mailbox
registers, CLKRUN# central resource control logic, integrated pull-up resistors are also implemented.
As a CardBus host mode, it supports only single PC Card slot and generates interface signals to PC Card power-
switch. CardBus Host Controller supports 16-bit PC Card (PCMCIA card) or CardBus PC Card. CardBus Host
Controller provides an address translation mechanism to map inbound PCI to local memory or peripherals and
outbound processor core or peripherals to PCI. Four independent 8-word deep FIFOs are implemented.
As a PCI/CardBus agent mode, it supports independent three address decoders and provides address translation
mechanism to map AHB local memory from PCI bus through three address bars and vice-versa. To support power
management, it complies with PCI Bus Power Management Interface Specification Rev. 1.1 and PCI Mobile
Design Guide Ver. 1.1. And also it supports DMA operation with two-channel dedicated DMA to enhance the
performance.
1-5
5 Page 
S3C2510A
PRODUCT OVERVIEW
Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued)
Group
System
Configurations
(21)
Pin Name
CLKMOD[1]
CLKMOD[0]
CPU_FREQ[2]
CPU_FREQ[1]
CPU_FREQ[0]
BUS_FREQ[2]
BUS_FREQ[1]
BUS_FREQ[0]
nRESET
TMODE
BIG
PCI_PCCDM
PCI_HOSTM
Pin No. I/O Type
AB4
AC2
I
AE1 I
AD1
AC3
AD2 I
AB3
AC1
AB2 I
AF3 I
W3 I
AA2 I
Y3 I
Pad
Type
phic
phic
phic
phis
phicd
phicd
phic
phic
Description
The CLKMOD pin determines internal
clock scheme of S3C2510A. When
CLKMOD is “00”, the nfast clock mode is
defined. In this mode, the same clock is
used as CPU clock and system clock.
When CLKMOD is “01” or “10”, the sync
mode is defined. In this mode, the system
clock is half frequency of the CPU clock.
When CLKMOD is "11", the async clock
mode is defined. In this mode, the CPU
clock and system clock can operate
independently as long as the CPU clock is
faster than system clock.
In this case, BUS_FREQ[2:0] pins should
be 3b’000 to select PCI PLL, 3b’001 to
select USB PLL for programmable setting.
CPU Clock Frequency Selection.
System Bus Clock Frequency Selection.
Not Reset. NRESET is the global reset
input for the S3C2510A and nRESET must
be held to "low" for at least 64 clock cycles
for digital filtering.
Test Mode. The TMODE pin setting is
interpreted as follows:
0 = normal operating mode
1 = chip test mode.
BIG endian mode select pin.
When this pin is set to “0”, the S3C2510A
operates in litte endian mode. When this
pin is set to “1”, the S3C2510A operates in
big endian mode.
PCI(1'b0) or PC Card(1'b1) Mode Select of
PCI & PC Card Controller
Host (1'b1) or Agent (1'b0) Mode Select of
PCI & PC Card Controller
1-11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet S3C2510A.PDF ] | |
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