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PDF S39421S Data sheet ( Hoja de datos )

Número de pieza S39421S
Descripción Hot Swap Voltage Controller
Fabricantes ETC 
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No Preview Available ! S39421S Hoja de datos, Descripción, Manual

SUMMIT
MICROELECTRONICS, Inc.
Hot Swap Voltage Controller
S39421
FEATURES
• Full Voltage Control for Hot Swap Applications
– Card Insertion Detection
– Platform Voltage Detection
– Card Voltage Sequencing
– 5 Volt, 12 Volt and 3.3 Volt
• 12 Volt FET Enable Outputs
– Allows use of Low On-resistance N-Channel
FETS
• Card Reset Generation Based on Out of Spec
Voltages
– Host Reset
• Programmable Slew Rate Control [250V/Sec
Default Rate]
• Supports 5 Volt, 3.3 Volt and Mixed Voltage
Cards
• Integrated 1K Bit E2PROM Memory
• Data Download™ Mode [Simplifies
Downloading of Configuration Memory into
Interface ASIC or MCU]
DESCRIPTION
The S39421 is a fully integrated hot swap controller
intended for use on add-in cards that may be inserted into
or removed from powered-on host platforms. The S39421
performs a variety of tasks starting with the validation of
proper card insertion and the presence of “in-spec” volt-
ages at the host platform interface.
Once power is switched on, the S39421 continues to
monitor the back-end power to the add-in card and the
host power supply. If either the 5V or 3.3V supplies drop
below Vtrip the S39421 will immediately assert the RE-
SET outputs and power-down the add-in card.
In addition to the power control for the add-in card, the
S39421 provides status signals that can be employed by
the host and for the control of bus interface components.
The on board E2PROM can be used as configuration
memory for the individual card or as general purpose
memory. The proprietary DataDownload mode provides
a more direct interface to the E2PROM for simplified
access by the add-in card’s controller or ASIC.
FUNCTIONAL BLOCK DIAGRAM
VCC5
PND1
VCC3
CARD_5V
CARD_3V
ASSOCIATE
EEPROM
Memory
Array
DD
DO
CS
SK
DI
MEMBER
+
- DRVREN
+
- Filter
+ Sequencing
- Logic
RESET
+ Timer
-
SGNL_VLD
CARD_V_VLD
RESET
RESET
PND2
ISLEW
Slew Rate
Control
VGATE3
VGATE5
2024 ILL2.1
SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com
© SUMMIT MICROELECTRONICS, Inc. 1999
2024 9.0 8/8/00
Characteristics subject to change without notice
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S39421S pdf
S39421
VTRIP5
VRVALID
VCC5
RESET
RESET
PND1+PND2
VGATE5 & VGATE3
DRVREN
CARD_5V & CARD_3V
tHSE
VCARD3
&
VCARD5
tSLEW
12V Level
tPURST
CARD_V_VLD
SGNL_VLD
HST_RST
[input]
RESET
[output]
<tPURST
=tPURST
2024 ILL3.1
HST_RST
[input]
>tPURST
RESET
[output]
2024 ILL31.0
FIGURE 1. CARD INSERTION AND HOST RESET TIMING DIAGRAM
5
2024 9.0 8/8/00

5 Page





S39421S arduino
S39421
SK
CS
AN AN1
DI
11
0
A0
tCS
STANDBY
HIGH-Z
tPD0
DO 0
tHZ
HIGH-Z
DN DN1
D1 D0
FIGURE 6. READ INSTRUCTION TIMING
2024 ILL20.0
SK
CS
AN AN-1
DI 1 0 1
A0 DN
D0
tCS
STATUS
VERIFY
STANDBY
tSV BUSY
tHZ
HIGH-Z
DO READY
HIGH-Z
tEW
2024 ILL21.0
FIGURE 7. WRITE INSTRUCTION TIMING
Erase/Write Enable and Disable
The memory powers up in the write disable state. Any
writing after power-up or after an EWDS (write disable)
instruction must first be preceded by the EWEN (write
enable) instruction. Once the write instruction is enabled,
it will remain enabled until power to the device is removed,
or the EWDS instruction is sent. The EWDS instruction
can be used to disable all S39421 write and clear instruc-
tions, and will prevent any accidental writing or clearing of
the device. Data can be read normally from the device
regardless of the write enable/disable status.
Write All
Upon receiving a WRAL command and data, the CS (Chip
Select) pin must be deselected for a minimum of 250ns
(tCSMIN). The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of
the S39421 can be determined by selecting the device
and polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
2024 9.0 8/8/00
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