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IDT71V67602133PFI fiches techniques PDF

Integrated Device Technology - 256K X 36/ 512K X 18 3.3V Synchronous SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs/ Single Cycle Deselect

Numéro de référence IDT71V67602133PFI
Description 256K X 36/ 512K X 18 3.3V Synchronous SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs/ Single Cycle Deselect
Fabricant Integrated Device Technology 
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IDT71V67602133PFI fiche technique
256K X 36, 512K X 18
3.3V Synchronous SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs, Single Cycle Deselect
IDT71V67602
IDT71V67802
Features
x 256K x 36, 512K x 18 memory configurations
x Supports high system speed:
– 166MHz 3.5ns clock access time
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
x LBO input selects interleaved or linear burst mode
x Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
x 3.3V core power supply
x Power down controlled by ZZ input
x 2.5V I/O supply (VDDQ)
x Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array.
Description
The IDT71V67602/7802 are high-speed SRAMs organized as
256K x 36/512K x 18. The IDT71V676/78 SRAMs contain write, data,
addressandcontrolregisters. InternallogicallowstheSRAMtogenerate
a self-timed write based upon a decision which can be left until the end of
the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V67602/7802 can provide four cycles of
dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
datawillbeavailabletotheuseronthenextthreerisingclockedges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The IDT71V67602/7802 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array (fBGA).
Pin Description Summary
A0-A18
Address Inputs
CE
CS0, CS1
Chip Enable
Chip Selects
OE Output Enable
GW Global Write Enable
BWE Byte Write Enable
BW1, BW2, BW3, BW4(1)
Individual Byte Write Selects
CLK Clock
ADV Burst Address Advance
ADSC
Address Status (Cache Controller)
ADSP
Address Status (Processor)
LBO Linear / Interleaved Burst Order
ZZ Sleep Mode
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
VDD, VDDQ
Core Power, I/O Power
VSS Ground
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V67802.
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
N/A
N/A
5311 tbl 01
©2002 Integrated Device Technology, Inc.
1
NOVEMBER 2002
DSC-5311/05

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