IDT71V65803 Datasheet PDF - Integrated Device Technology
| Part Number | IDT71V65803 | |
| Description | 256K x 36/ 512K x 18 3.3V Synchronous ZBT SRAMs | |
| Manufacturers | Integrated Device Technology | |
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256K x 36, 512K x 18
3.3V Synchronous ZBT™ SRAMs
ZBT™ Feature
3.3V I/O, Burst Counter
Pipelined Outputs
IDT71V65603
IDT71V65803
Features
x 256K x 36, 512K x 18 memory configurations
x Supports high performance system speed - 150MHz
(3.8ns Clock-to-Data Access)
x ZBTTM Feature - No dead cycles between write and read cycles
x Internally synchronized output buffer enable eliminates the
need to control OE
x Single R/W (READ/WRITE) control pin
x Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
x 4-word burst capability (interleaved or linear)
x Individual byte write (BW1 - BW4) control (May tie active)
x Three chip enables for simple depth expansion
x 3.3V power supply (±5%)
x 3.3V I/O Supply (VDDQ)
x Power down controlled by ZZ input
x Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array(fBGA).
Description
The IDT71V65603/5803 are 3.3V high-speed 9,437,184-bit
(9 Megabit) synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or writes and
reads.Thus,theyhavebeengiventhenameZBTTM,orZeroBusTurnaround.
Address and control signals are applied to the SRAM during one clock
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.
The IDT71V65603/5803 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
AClockEnable(CEN)pinallowsoperationoftheIDT71V65603/5803to
besuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen
(CEN)ishighandtheinternaldeviceregisterswillholdtheirpreviousvalues.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
todeselectthedevicewhendesired.Ifanyoneofthesethreearenotasserted
when ADV/LD is low, no new memory operation can be initiated. However,
anypendingdatatransfers(readsorwrites)willbecompleted.Thedatabus
will tri-state two cycles after chip is deselected or a write is initiated.
The IDT71V65603/5803 have an on-chip burst counter. In the burst
mode, the IDT71V65603/5803 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
externaladdress(ADV/LD=LOW) orincrementtheinternalburstcounter
(ADV/LD = HIGH).
The IDT71V65603/5803 SRAM utilize IDT's latest high-performance
CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm100-
pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and
165 fine pitch ball grid array (fBGA) .
Pin Description Summary
A0-A18
CE1, CE2, CE2
OE
R/W
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
CEN Clock Enable
BW1, BW2, BW3, BW4
Individual Byte Write Selects
CLK
ADV/LD
Clock
Advance burst address / Load new address
LBO Linear / Interleaved Burst Order
ZZ Sleep Mode
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
VDD, VDDQ
Core Power, I/O Power
VSS Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Asynchronous
Synchronous
Static
Static
5304 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
©2002 Integrated Device Technology, Inc.
1
DECEMBER 2002
DSC-5304/05
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IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Grade
Temperature(1) VSS
VDD
VDDQ
Commercial 0° C to +70° C 0V
3.3V± 5%
3.3V± 5%
Industrial -40°C to +85°C 0V
3.3V± 5%
3.3V± 5%
NOTES:
1. TA is the "instant on" case temperature.
5304 tbl 05
Pin Configuration - 256K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDDQ
I/O22
I/O23
VDD(1)
VDD
VDD(1)
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
1 80 I/OP2
2 79 I/O15
3 78 I/O14
4 77 VDDQ
5 76 VSS
6 75 I/O13
7 74 I/O12
8 73 I/O11
9 72 I/O10
10 71 VSS
11 70 VDDQ
12 69 I/O9
13 68 I/O8
14 67 VSS
15 66 VDD(1)
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VDD
ZZ
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
5304 drw 02
,
Top View
100 TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pin 84 is reserved for a future 16M.
3. DNU=Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG pins: TMS, TDI, TDO and TCK. The
current die revision allows these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
6.452
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| Information | Total 26 Pages | |
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| Download | [ IDT71V65803.PDF Datasheet ] | |
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