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PDF IDT71V509S66Y Data sheet ( Hoja de datos )
| Número de pieza | IDT71V509S66Y | |
| Descripción | 128K x 8 3.3V SYNCHRONOUS SRAM WITH ZBTO AND FLOW-THROUGH OUTPUT | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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Integrated Device Technology, Inc.
128K x 8 3.3V SYNCHRONOUS SRAM
WITH ZBT™ AND FLOW-THROUGH
OUTPUT
ADVANCE
INFORMATION
IDT71V509
FEATURES:
• 128K x 8 memory configuration
• High speed - 66 MHz (9 ns Clock-to-Data Access)
• Flow-Through Output
• No dead cycles between Write and Read Cycles
• Low power deselect mode
• Single 3.3V power supply (±5%)
• Packaged in 44-lead SOJ
DESCRIPTION:
The IDT71V509 is a 3.3V high-speed 1,024,576-bit syn-
chronous SRAM organized as 128K x 8. It is designed to
eliminate dead cycles when turning the bus around between
reads and writes, or writes and reads. Thus, it has been given
the name ZBT™ , or Zero Bus Turnaround™ .
Addresses and control signals are applied to the SRAM
during one clock cycle, and one clock cycle later its associated
data cycle occurs, be it read or write.
The IDT71V509 contains data, address, and control signal
registers. Output Enable is the only asynchronous signal, and
can be used to disable the output at any time.
A Clock Enable (CEN) pin allows operation of the IDT71V509
to be suspended as long as necessary. All synchronous
inputs are ignored when CEN is high. A Chip Select (CS) pin
allows the user to deselect the device when desired. If CS is
high, no new memory operation is initiated, but any pending
data transfers (reads and writes) will still be completed.
The IDT71V509 utilizes IDT's high-performance 3.3V CMOS
process, and is packaged in a JEDEC Standard 400-mil 44-
lead small outline J-lead plastic package (SOJ) for high board
density.
FUNCTIONAL BLOCK DIAGRAM
Address
DQ
Control
(WE, CS, CEN)
DQ
Address
SRAM
Control
DI DO
DQ
Control Logic
Clk
Mux Sel
Clock
OE Gate
Data
The IDT logo is a registered trademark and CacheRAM, Zero Bus Turnaround and ZBTare trademarks of Integrated Device Technology, Inc.
Pentium is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
11.3
3618 drw 01
AUGUST 1996
DSC-3618/1
1
1 page  
IDT71V509
128K X 8 3.3V SYNCHRONOUS SRAM WITH ZBT™ AND FLOW-THROUGH OUTPUT
COMMERCIAL TEMPERATURE RANGE
READ OPERATION WITH CHIP SELECT USED
Cycle Address
WE CS CEN OE I/O
nX
XH L X ?
n+1 X
XH L X Z
n+2 A2
HL LXZ
n+3 X
X H L L D2
n+4 A4
HL LXZ
n+5 X
X H L L D4
n+6 X
XH L X Z
n+7 A7
HL LXZ
n+8 X
X H L L D7
n+9 X
XH L X Z
H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance
Comments
Deselected
Deselected
Address and Control meet setup
Deselected, Contents of Address A2 Read Out
Address and Control meet setup
Deselected, Contents of Address A4 Read Out
Deselected
Address and Control meet setup
Deselected, Contents of Address A7 Read Out
Deselected
3618 tbl 06
WRITE OPERATION WITH CHIP SELECT USED
Cycle Address
WE CS CEN OE I/O
nX
XH L X ?
n+1 X
XH L X Z
n+2 A2
L L LXZ
n+3 X
X H L X D2
n+4 A4
L L LXZ
n+5 X
X H L X D4
n+6 X
XH L X Z
n+7 A7
L L LXZ
n+8 X
X X L X D7
n+9 X
XX L X Z
H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance
Comments
Deselected
Deselected
Address and Control meet setup
Deselected, New Data Drives SRAM Inputs
Address and Control meet setup
Deselected, New Data Drives SRAM Inputs
Deselected
Address and Control meet setup
Deselected, New Data Drives SRAM Inputs
Deselected
3618 tbl 07
11.3 5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet IDT71V509S66Y.PDF ] | |
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