DataSheetWiki


IDT71V35761YS183BG fiches techniques PDF

Integrated Device Technology - 128K x 36/ 256K x 18 3.3V Synchronous SRAMs 3.3V I/O/ Pipelined Outputs Burst Counter/ Single Cycle Deselect

Numéro de référence IDT71V35761YS183BG
Description 128K x 36/ 256K x 18 3.3V Synchronous SRAMs 3.3V I/O/ Pipelined Outputs Burst Counter/ Single Cycle Deselect
Fabricant Integrated Device Technology 
Logo Integrated Device Technology 





1 Page

No Preview Available !





IDT71V35761YS183BG fiche technique
128K x 36, 256K x 18
3.3V Synchronous SRAMs
3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect
IDT71V35761S
IDT71V35781S
IDT71V35761SA
IDT71V35781SA
Features
x 128K x 36, 256K x 18 memory configurations
x Supports high system speed:
Commercial:
– 200MHz 3.1ns clock access time
Commercial and Industrial:
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time
x LBO input selects interleaved or linear burst mode
x Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
x 3.3V core power supply
x Power down controlled by ZZ input
x 3.3V I/O
x Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
x Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array
Pin Description Summary
Description
The IDT71V35761/781 are high-speed SRAMs organized as
128K x 36/256K x 18. The IDT71V35761/781 SRAMs contain write, data,
addressandcontrolregisters. InternallogicallowstheSRAMtogenerate
a self-timed write based upon a decision which can be left until the end of
the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V35761/81 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
datawillbeavailabletotheuseronthenextthreerisingclockedges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The IDT71V35761/781 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array.
A0-A17
Address Inputs
Input Synchronous
CE Chip Enable
Input Synchronous
CS0, CS1
Chip Selects
Input Synchronous
OE Output Enable
Input Asynchronous
GW Global Write Enable
Input Synchronous
BWE Byte Write Enable
Input Synchronous
BW1, BW2, BW3, BW4(1)
Individual Byte Write Selects
Input Synchronous
CLK Clock
Input N/A
ADV Burst Address Advance
Input Synchronous
ADSC
Address Status (Cache Controller)
Input Synchronous
ADSP
Address Status (Processor)
Input Synchronous
LBO Linear / Interleaved Burst Order
Input DC
TMS Test Mode Select
Input Synchronous
TDI Test Data Input
Input Synchronous
TCK Test Clock
Input N/A
TDO Test Data Output
Output
Synchronous
TRST
JTAG Reset (Optional)
Input Asynchronous
ZZ Sleep Mode
Input Asynchronous
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
I/O Synchronous
VDD, VDDQ
Core Power, I/O Power
Supply
N/A
NVOSTSE:
Ground
1. BW3 and BW4 are not applicable for the IDT71V35781.
©2003 Integrated Device Technology, Inc.
1
Supply
N/A
5301 tbl 01
JUNE 2003
DSC-5301/03

PagesPages 22
Télécharger [ IDT71V35761YS183BG ]


Fiche technique recommandé

No Description détaillée Fabricant
IDT71V35761YS183BG 128K x 36/ 256K x 18 3.3V Synchronous SRAMs 3.3V I/O/ Pipelined Outputs Burst Counter/ Single Cycle Deselect Integrated Device Technology
Integrated Device Technology
IDT71V35761YS183BGI 128K x 36/ 256K x 18 3.3V Synchronous SRAMs 3.3V I/O/ Pipelined Outputs Burst Counter/ Single Cycle Deselect Integrated Device Technology
Integrated Device Technology
IDT71V35761YS183BQ 128K x 36/ 256K x 18 3.3V Synchronous SRAMs 3.3V I/O/ Pipelined Outputs Burst Counter/ Single Cycle Deselect Integrated Device Technology
Integrated Device Technology
IDT71V35761YS183BQI 128K x 36/ 256K x 18 3.3V Synchronous SRAMs 3.3V I/O/ Pipelined Outputs Burst Counter/ Single Cycle Deselect Integrated Device Technology
Integrated Device Technology

US18650VTC5A

Lithium-Ion Battery

Sony
Sony
TSPC106

PCI Bus Bridge Memory Controller

ATMEL
ATMEL
TP9380

NPN SILICON RF POWER TRANSISTOR

Advanced Semiconductor
Advanced Semiconductor


www.DataSheetWiki.com    |   2020   |   Contactez-nous  |   Recherche