IDT71V3556SA100BGG Datasheet PDF - Integrated Device Technology
| Part Number | IDT71V3556SA100BGG | |
| Description | 128K x 36/ 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O/ Burst Counter Pipelined Outputs | |
| Manufacturers | Integrated Device Technology | |
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128K x 36, 256K x 18
3.3V Synchronous ZBT SRAMs
3.3V I/O, Burst Counter
Pipelined Outputs
IDT71V3556S
IDT71V3558S
IDT71V3556SA
IDT71V3558SA
Features
x 128K x 36, 256K x 18 memory configurations
x Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
x ZBTTM Feature - No dead cycles between write and read
cycles
x Internally synchronized output buffer enable eliminates the
need to control OE
x Single R/W (READ/WRITE) control pin
x Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
x 4-word burst capability (interleaved or linear)
x Individual byte write (BW1 - BW4) control (May tie active)
x Three chip enables for simple depth expansion
x 3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)
x Optional- Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
x Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
Description
The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit) synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBTTM, or
Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later the associated data cycle occurs, be it
read or write.
The IDT71V3556/58 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V3556/58
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold
their previous values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will be
completed. The data bus will tri-state two cycles after chip is deselected
or a write is initiated.
Pin Description Summary
A0-A17
CE1, CE2, CE2
OE
R/W
CEN
BW1, BW2, BW3, BW4
CLK
ADV/LD
LBO
TMS
TDI
TCK
TDO
TRST
ZZ
I/O0-I/O31, I/OP1-I/OP4
VDD, VDDQ
VSS
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance b urst address / Load new address
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Test Clock
Test Data Output
JTAG Reset (Optional)
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
©2004 Integrated Device Technology, Inc.
1
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Synchronous
N/A
Synchronous
Asynchronous
Synchronous
Synchronous
Static
Static
5281 tbl 01
SEPTEMBER 2004
DSC-5281/08
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IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Grade
Temperature(1)
VSS
VDD
VDDQ
Commercial
0°C to +70°C
0V 3.3V± 5% 3.3V± 5%
Industrial
-40°C to +85°C 0V 3.3V± 5% 3.3V± 5%
NOTES:
1. TA is the "instant on" case temperature.
5281 tbl 05
Pin Configuration - 128K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDDQ
I/O22
I/O23
VDD(1)
VDD
VDD(1)
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
VDD(1)
VDD
VSS/ZZ(3)
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
,VSS
VDDQ
I/O1
I/O0
I/OP1
5281 drw 02
Top View
100 TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this
pin supports ZZ (sleep mode).
6.452
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| Information | Total 28 Pages | |
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Featured Datasheets
| Part Number | Description | MFRS |
| IDT71V3556SA100BGG | The function is 128K x 36/ 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O/ Burst Counter Pipelined Outputs. Integrated Device Technology | |
| IDT71V3556SA100BGGI | The function is 128K x 36/ 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O/ Burst Counter Pipelined Outputs. Integrated Device Technology | |
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