IDT71V2548SA133BGI Datasheet PDF - Integrated Device Technology
| Part Number | IDT71V2548SA133BGI | |
| Description | 128K x 36/ 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs | |
| Manufacturers | Integrated Device Technology | |
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128K x 36, 256K x 18
3.3V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
IDT71V2546S
IDT71V2548S
IDT71V2546SA
IDT71V2548SA
Features
x 128K x 36, 256K x 18 memory configurations
x Supports high performance system speed - 150 MHz
(3.8 ns Clock-to-Data Access)
x ZBTTM Feature - No dead cycles between write and read
cycles
x Internally synchronized output buffer enable eliminates the
need to control OE
x Single R/W (READ/WRITE) control pin
x Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
x 4-word burst capability (interleaved or linear)
x Individual byte write (BW1 - BW4) control (May tie active)
x Three chip enables for simple depth expansion
x 3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)
x Optional Boundary Scan JTAG Interface (IEEE1149.1
complaint)
x Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine
pitch ball grid array
Description
The IDT71V2546/48 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit) synchronous SRAMS. They are designed to eliminate dead bus cycles
when turning the bus around between reads and writes, or writes and
reads. Thus, they have been given the name ZBTTM, or Zero Bus
Turnaround.
Pin Description Summary
A 0-A 17
Address Inputs
Address and control signals are applied to the SRAM during one clock
cycle, and two cycles later the associated data cycle occurs, be it read
or write.
The IDT71V2546/48 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V2546/48 to
be suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state two cycles after chip is deselected or a write is
initiated.
The IDT71V2546/48 has an on-chip burst counter. In the burst mode,
the IDT71V2546/48 can provide four cycles of data for a single address
presented to the SRAM. The order of the burst sequence is defined by the
LBO input pin. TheLBO pin selects between linear and interleaved burst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
The IDT71V2546/48 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array (fBGA).
Input Synchronous
CE1, CE2, CE2
Chip Enables
Input Synchronous
OE Output Enable
Input Asynchronous
R/W Read/Write Signal
Input Synchronous
CEN Clock Enable
Input Synchronous
BW1, BW2, BW3, BW4
Individual Byte Write Selects
Input Synchronous
CLK Clock
Input N/A
ADV/LD
Adv ance burst address / Load new address
Input Synchronous
LBO Linear / Interleaved Burst Order
Input Static
TMS Test Mode Select
Input Synchronous
TDI Test Data Input
Input Synchronous
TCK Test Clock
Input N/A
TDO Test Data Output
Output
Synchronous
TRST
JTAG Reset (Optional)
Input Asynchronous
ZZ Sleep Mode
Input Synchronous
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
I/O Synchronous
VDD, VDDQ
Core Power, I/O Power
Supply
Static
VSS Ground
Supply
Static
©2004 Integrated Device Technology, Inc.
1
5294 tbl 01
SEPTEMBER 2004
DSC-5294/04
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IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Grade
Temperature(1)
VSS
VDD
VDDQ
Commercial
0°C to +70°C
0V 3.3V± 5% 2.5V± 5%
Industrial
-40°C to +85°C 0V 3.3V± 5% 2.5V± 5%
NOTE:
1. TA is the "instant on" case temperature.
5294 tbl 05
Pin Configuration 128K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDDQ
I/O22
I/O23
VDD(1)
VDD
VDD(1)
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
1 80 I/OP2
2 79 I/O15
3 78 I/O14
4 77 VDDQ
5 76 VSS
6 75 I/O13
7 74 I/O12
8 73 I/O11
9 72 I/O10
10 71 VSS
11 70 VDDQ
12 69 I/O9
13 68 I/O8
14 67 VSS
15 66 VDD(1)
16 65 VDD
17 64 VSS/ZZ(3)
18 63 I/O7
19 62 I/O6
20 61 VDDQ
21 60 VSS
22 59 I/O5
23 58 I/O4
24 57 I/O3
25 56 I/O2
26 55 VSS
27 54 VDDQ
28 53 I/O1
29 52 I/O0
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/OP1
5294 drw 02
,
Top View
100 TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this
pin supports ZZ (sleep mode).
6.452
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Featured Datasheets
| Part Number | Description | MFRS |
| IDT71V2548SA133BG | The function is 128K x 36/ 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs. Integrated Device Technology | |
| IDT71V2548SA133BGI | The function is 128K x 36/ 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs. Integrated Device Technology | |
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